In the context of today’s rapidly changing world, multimedia data have been used more and more widely in human being’s life. Large amounts of multimedia data have been produced and diffused in several fields. Thus, various encryption approaches for multimedia applications and services have been proposed in order to gratify different applications. Many video encryption algorithms combine encryption within the video coding algorithm to satisfy both video compression and encryption. In fact, the H.264 Advanced Video Coding (H.264/AVC) standard is one of the most frequently used formats for video compression. In this paper, we propose a novel selective encryption method that combines two encryption techniques and deals with the requirements of the real-time applications. The proposed scheme achieves video encryption using a chaos key generator and the AES (Advanced Encryption Standard) algorithm. To evaluate the proposed scenarios, we calculated the hardware performances and conducted five different security analyses.

With the development of communication technology, the internet of things and the rapid augment of their applications and services, the demand for indoor localization is increasing. RFID based indoor localization system is a good solution for these applications and services. However, due to the complex multi-path interference of indoor environment, most of the localization methods have a low positioning accuracy. In this paper, we present an enhanced holographic RFID localization method for static tags in indoor environment by using four moving RFID readers. The obtained results show the power of our proposed method in term of positioning accuracy for wide localization area.

The Internet of Things is changing all sectors such as manufacturing, agriculture, city infrastructure, and the automotive industry. All these applications ask for secure processors that can be embedded in the IoT devices. Furthermore, these devices are restricted in terms of computing capabilities, memory, and power consumption. A major challenge is how to meet the need for security in such resource-constrained devices. This paper presents a customized version of LEON3, the ReonV RISCV (Reduced Instruction Set Computer-five) processor, dedicated for IoT applications that has strong effective security mechanisms built in at the design stage. Firstly, efficient lightweight cipher designs are elaborated and validated. Then, the proposed cryptographic instructions (PRESENT and PRINCE) are integrated into the default instruction set architecture of the ReonV processor core. The instruction set extensions (ISE) of lightweight cipher modules can be instantiated in software routines exactly as the instructions of the base architecture. A single instruction is needed to implement a full lightweight cryptographic instruction. The customized ReonV RISCV processor is implemented on a Xilinx FPGA platform and is evaluated for Slice LUTs plus FF-pairs, frequency, and throughput. Obtained results show that our proposed concepts not only can achieve good encryption results with high performance and reduced cost but also are secure enough to resist against the most common attacks.

In telemedicine applications, sensitive and private patients' information is collected and transmitted via a telecommunication system. To assure the security services of the exchanged medical images, improved cryptographic algorithms should be designed to protect private information against attacks. In this paper, we propose an efficient cryptosystem for medical image encryption and authentication. The cryptosystem is an Improved Advanced Encryption Standard (IAES) - Elliptic Curve Digital Signature Algorithm (ECDSA) hybrid scheme that uses symmetric and asymmetric approaches. The first one is used to encrypting the image. The second one is used to encrypting the initial secret key and owner's signature that permit authentication. The implementation on a Cyclone III FPGA uses 18.594 of total logic elements, 17.820 of total combinatorial functions, and 131.616 of total memory. It runs at a frequency of 147.16 MHz, consumes 171.16 mW and can achieve excellent throughput of 1.71 Gb / s. Results prove that the proposed cipher framework is appropriate for embedded systems respecting both real-time performance and resources constrained. The security analysis is successfully performed and experimental results prove that the suggested technique provides the basis of cryptography.

Atrial Fibrillation (AF) is a health-threatening condition, which is a violation of the heart rhythm that can lead to heart-related complications. Remarkable interest has been given to ECG signals analysis for AF detection in an early stage. In this context, we propose an artificial neural network ANN application to classify ECG signals into three classes, the first presents Normal Sinus Rhythm NSR, the second depicts abnormal signal with Atrial Fibrillation (AF) and the third shows noisy ECG signals. Accordingly, we achieve 93.1% accuracy classification results, 95.1% of sensitivity, 90.5% of specificity and 98%. Furthermore, we yield a value of zero error and a low value of cross entropy, which prove the robustness of the proposed ANN model architecture. Thus, we outperform the state of the art by achieving high accuracy classification without pre-processing step and without high level of feature extraction, and then we enable clinicians to determine automatically the class of each patient ECG signal.

Asymmetric cryptography is inherently slow because of its associated complex computing, while symmetric cryptography is speedy. However, the latter is suffering from a serious gap which is secure key exchange. To deal with this problem, we suggest an efficient hybrid AES-ECC cryptosystem combining the benefits of the symmetric advanced encryption standard (AES) to speed-up data encryption and the asymmetric elliptic curve cryptography (ECC) to secure the symmetric key session interchange. The proposed hybrid AES-ECC cryptosystem uses a co-design approach and relies on AES-ECC optimisations. We fundamentally mix the matrix multiplication of the AES MixColumns with the S-box allowing for very fast software implementation (on NIOS-II processor). Then, we propose an optimised ECC hardware architecture based on López-Dahab scalar multiplication (on Cyclone IV.E). The implementation results of the proposed cryptosystem afford an interesting trade-off between area, speed, and power and can be used for information and computer security.

The recent expansion of the Internet of Things is creating a new world of smart devices in which security implications are very significant. Besides the claimed security level, the IoT devices are usually featured with constrained resources, such as low computation capability, low memory, and limited battery. Lightweight cryptographic primitives are proposed in the context of IoT while considering the trade-off between security guarantee and good performance. In this paper, we present optimized hardware, lightweight cryptographic designs, of 32-bit datapath, LED 64/128, SIMON 64/128, and SIMECK 64/128 algorithms, for constrained devices. Our proposed designs are investigated on Spartan-3, Spartan-6, and Zynq-7000 FPGA platforms in terms of area, speed, efficiency, and power consumption. The proposed designs achieved a high throughput up to 891.99 Mbps, 838.95 Mbps, and 210.13 Mbps for SIMECK 64/128, SIMON 64/128, and LED 64/128 on Zynq-7000, respectively. A deep comparison between our three proposed designs is elaborated on different FPGA families for adequate FPGAs-based application deployment. Test results and security analysis show that not only can our proposed designs achieve good encryption results with high performance and a low reduced cost but also they are secure enough to resist statistical attacks.

In cryptography, Cipher Block Chaining (CBC) mode of operation presents a very popular way of encryption that is used in numerous applications. In our previous research work, we have been proven that, under some conditions, this mode of operation can exhibit a chaotic behavior according to the reputed definition of Devaney. The quantitative study of this chaotic CBC has been deepened later by evaluating both its level of sensibility and of expansivity. In this paper, our objective is now to further develop the evaluation of the CBC dynamics, by obtaining a complete topological study of this mode of operation. Such an evaluation encompasses both the qualitative property of topological mixing and its level of topological entropy, which is indeed a quantitative measure of disorder.

The number of resource-limited wireless devices utilized in many areas of Internet of Things is growing rapidly; there is a concern about privacy and security. Various lightweight block ciphers are proposed; this work presents a modified lightweight block cipher algorithm. A Linear Feedback Shift Register is used to replace the key generation function in the XTEA1 Algorithm. Using the same evaluation conditions, we analyzed the software implementation of the modified XTEA using FELICS (Fair Evaluation of Lightweight Cryptographic Systems) a benchmarking framework which calculates RAM footprint, ROM occupation and execution time on three largely used embedded devices: 8-bit AVR microcontroller, 16-bit MSP microcontroller and 32-bit ARM microcontroller. Implementation results show that it provides less software requirements compared to original XTEA. We enhanced the security level and the software performance.

In this paper we present the design considerations of lightweight encryption algorithm. Our aim is to demonstrate how to achieve lightweight block ciphers efficient software performance for low-resource embedded devices. Several lightweight block ciphers are proposed; we selected the most recent and suitable for low-resource embedded systems such as RFID tags. In this work, we analyzed the software implementation of lightweight block ciphers using FELICS (Fair Evaluation of Lightweight Cryptographic Systems) a benchmarking framework which computes execution time, RAM consumption and ROM occupation on two largely used devices: 8-bit AVR microcontroller and 16-bit MSP microcontroller. Using the same evaluation conditions, we selected the most suitable ciphers for low-resource devices.

Pairing-based cryptography has got a lot of attention the last years, since the proposition of the tripartite key exchange. The best type of pairing is optimal ate pairing over Barreto-Naehrig curves which are based on two steps: Miller Loop and final exponentiation. Most of the researches were done for the Miller Loop. In this paper, we present the different methods for computing the hard part of the final exponentiation of optimal ate pairings based on a hard mathematical study. Using a comparative study based on the temporary number and memory resources, we will choose the best method to be then implemented in Matlab Software. Thus, the best one is Devigili et al. method presenting a reduced complexity and required number of registers.

Recently, a lot of progress has been made in the implementation of asymmetric cryptography such that RSA or ECC (Elliptic Curve Cryptography) in both hardware and software. The Residue Number Systems (RNS) offer, many features make it very useful in cryptographic applications. Since the modular multiplication is the main operation, in this paper, we describe a Montgomery modular multiplication algorithm based on RNS. Then we implemented our design in TM i3 CPU, it computed the modular multiplication in only 9 ms (latency) and achieving maximum throughput of 528.

The main applications of the hash functions are met in the fields of communication's integrity and signature authentication. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. We propose a configurable secure hash algorithm (SHA) processor for extended signature authentication. This paper investigates different optimizations algorithms of recent techniques that have been proposed in the literature. In our implementation based on Xilinx Virtex FPGAs, the throughput of SHA processor is equal to 1296 Mbit/s. Speed/area results from these processors are analyzed and shown to compare favorably with other FPGA-based implementations. A fastest data throughput is achieved by our optimized algorithm