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Yuanfeng Peng

dblp:19/8277 · DBLP profile ↗
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10ranked-venue papers
4as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 1 first-authorSystems, architecture and hardware · 3 · 2 first-authorTheory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
GPUs and heterogeneous computing · 52% Parallel and multicore computing · 32% Processor architecture and microarchitecture · 16%
Software engineering, system software, and programming languages
2 papers
Concurrent programming · 94% Program analysis · 6%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming › concurrency bug detection
data race detection
0.622018
CURD: a dynamic CUDA race detector · PLDI 2018
BARRACUDA: binary-level analysis of runtime RAces in CUDA programs · PLDI 2017
GPUs and heterogeneous computing › GPU programming
CUDA
0.622018
CURD: a dynamic CUDA race detector · PLDI 2018
BARRACUDA: binary-level analysis of runtime RAces in CUDA programs · PLDI 2017
Concurrent programming › concurrency bug detection › data race detection
GPU data race detection
0.312018
CURD: a dynamic CUDA race detector · PLDI 2018
GPUs and heterogeneous computing
GPU programming
0.312018
CURD: a dynamic CUDA race detector · PLDI 2018
Concurrent programming
concurrency bugs
0.312017
BARRACUDA: binary-level analysis of runtime RAces in CUDA programs · PLDI 2017
Parallel and multicore computing › concurrent programming
concurrency bugs
0.312017
PARSNIP: performant architecture for race safety with no impact on precision · MICRO 2017
Parallel and multicore computing › parallel computing › parallel program debugging
data race detection
0.312017
PARSNIP: performant architecture for race safety with no impact on precision · MICRO 2017
Processor architecture and microarchitecture › debugging support
race detection hardware
0.312017
PARSNIP: performant architecture for race safety with no impact on precision · MICRO 2017
Concurrent programming
concurrency bug detection
0.112018
CURD: a dynamic CUDA race detector · PLDI 2018
Program analysis
dynamic analysis
0.112017
BARRACUDA: binary-level analysis of runtime RAces in CUDA programs · PLDI 2017

Methods — techniques the papers use, named apart from their topics

dynamic analysis · 0.9compiler instrumentation · 0.7binary-level analysis · 0.6
YearPublicationVenuePosition
2018 SLIMFAST: Reducing Metadata Redundancy in Sound and Complete Dynamic Data Race Detection
abstract
Data races are one of the main culprits behind the complexity of multithreaded programming. Existing data race detectors require large amounts of metadata for each program variable to perform their analyses. The SLIMFAST system exploits the insight that there is a large amount of redundancy in this metadata: many program variables often have identical metadata state. By sharing metadata across variables, a large reduction in space usage can be realized. SLIMFAST uses immutable metadata to safely support metadata sharing across threads while also accelerating concurrency control. SLIMFAST's lossless metadata compression achieves these benefits while preserving soundness and completeness. Across a range of benchmarks from Java Grande, DaCapo, NAS Parallel Benchmarks and Oracle's BerkeleyDB Java Edition, SLIMFAST is able to reduce memory consumption by 1.83x on average, and up to 4.90x for some benchmarks, compared to the state-of-the-art FASTTRACK system. By improving cache locality and simplifying concurrency control, SLIMFAST also accelerates data race detection by 1.40x on average, and up to 8.8x for some benchmarks, compared to FASTTRACK.
Yuanfeng Peng, Christian DeLozier, Ariel Eizenberg, William Mansky, Joseph Devietti
IPDPS1
2018 CURD: a dynamic CUDA race detector
abstract
As GPUs have become an integral part of nearly every pro- cessor, GPU programming has become increasingly popular. GPU programming requires a combination of extreme levels of parallelism and low-level programming, making it easy for concurrency bugs such as data races to arise. These con- currency bugs can be extremely subtle and di cult to debug due to the massive numbers of threads running concurrently on a modern GPU. While some tools exist to detect data races in GPU pro- grams, they are often prohibitively slow or focused only on a small class of data races in shared memory. Compared to prior work, our race detector, CURD, can detect data races precisely on both shared and global memory, selects an appropriate race detection algorithm based on the synchronization used in a program, and utilizes efficient compiler instrumentation to reduce performance overheads. Across 53 benchmarks, we find that using CURD incurs an aver- age slowdown of just 2.88x over native execution. CURD is 2.1x faster than Nvidia’s CUDA-Racecheck race detector, de- spite detecting a much broader class of races. CURD finds 35 races across our benchmarks, including bugs in established benchmark suites and in sample programs from Nvidia.
Yuanfeng Peng, Vinod Grover, Joseph Devietti
PLDI1
2017 Verifying dynamic race detection
abstract
Writing race-free concurrent code is notoriously difficult, and data races can result in bugs that are difficult to isolate and reproduce. Dynamic race detection can catch data races that cannot (easily) be detected statically. One approach to dynamic race detection is to instrument the potentially racy code with operations that store and compare metadata, where the metadata implements some known race detection algorithm (e.g. vector-clock race detection). In this paper, we describe the process of formally verifying several algorithms for dynamic race detection. We then turn to implementations, laying out an instrumentation pass for race detection in a simple language and presenting a mechanized formal proof of its correctness: all races in a program will be caught by the instrumentation, and all races detected by the instrumentation are possible in the original program.
William Mansky, Yuanfeng Peng, Steve Zdancewic, Joseph Devietti
CPP2
2017 PARSNIP: performant architecture for race safety with no impact on precision
abstract
Data race detection is a useful dynamic analysis for multithreaded programs that is a key building block in record-and-replay, enforcing strong consistency models, and detecting concurrency bugs. Existing software race detectors are precise but slow, and hardware support for precise data race detection relies on assumptions like type safety that many programs violate in practice.
Yuanfeng Peng, Benjamin P. Wood, Joseph Devietti
MICRO1
2017 BARRACUDA: binary-level analysis of runtime RAces in CUDA programs
abstract
GPU programming models enable and encourage massively parallel programming with over a million threads, requiring extreme parallelism to achieve good performance. Massive parallelism brings significant correctness challenges by increasing the possibility for bugs as the number of thread interleavings balloons. Conventional dynamic safety analyses struggle to run at this scale.
Ariel Eizenberg, Yuanfeng Peng, Toma Pigli, William Mansky, Joseph Devietti
PLDI2
2016 HV2M: A novel approach to boost inter-VM network performance for Xen-based HVMs
Yuebin Bai, Yongwang Zhao, Duo Lu, Yuanfeng Peng, Minxuan Zhou
J. Syst. Softw.6
2014 BIDS: Bridgehead-Employed Image Distribution System for Cloud Data Centers
Zhongzhao Wang, Yuebin Bai, Jihong Ma, Duo Lv, Yuanfeng Peng
NPC6
2013 A high performance inter-domain communication approach for virtual machines
Yuebin Bai, Duo Lv, Yuanfeng Peng
J. Syst. Softw.5
2012 SAME: A students' daily activity mobility model for campus delay-tolerant networks
abstract
Mobility model plays a crucial part in wireless network simulation or mathematical analysis, especially for human mobility because real mobility network constructed by human is hard to trace, measure or apply to different scenarios. For delay-tolerant networks, mobility model also affects the frequency and duration of opportunities for data transfer between nodes, which is a key factor of network performance, so whether we can choose a model according to realistic scenes is important for the accuracy and practicability of simulation. In this paper, we propose a new mobility model of students' daily activities based on the analysis and conclusion of students' habits and customs in campus environments, which is able to produce inter-contact time, contact time distribution and other contact information. We validate the movement model by using the ONE simulator comparing with other movement models and tracing data from real-world measurement experiments. Results show that SAME is consistent with actual student behavior characteristics.
Yuebin Bai, Wentao Yang 0001, Yuanfeng Peng, Chongguang Bi
APCC4
2010 Capacity sensitivity of the cooperative MIMO relay network over spatially correlated channels
abstract
In this paper, we focus on the capacity sensitivity of the cooperative MIMO relay network over spatially correlated channels. We study and compare the capacity loss of MMSE, MF, SVD, AF and ZF relaying schemes over Rayleigh flat fading channels where antennas of the source or destination terminal are correlated. Simulation results show that the MF relaying scheme is most sensitive for all existing relaying schemes. In order to improve the performance of capacity sensitivity for the MF relaying scheme, this paper proposes a modified MF relaying scheme, which is analogous to the MF relaying scheme but has much less capacity sensitivity.
Yuanfeng Peng, Youzheng Wang
IWCMC1