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Yiannis Iosifidis

dblp:19/8314 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 77% Memory systems · 23%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization › parallelization
automatic parallelization
0.012010
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms · DAC 2010
Memory systems
memory hierarchy
0.012010
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms · DAC 2010

Methods — techniques the papers use, named apart from their topics

static and dynamic memory optimization · 0.2parallelization · 0.2
YearPublicationVenuePosition
2010 A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
abstract
The key characteristic of next generation embedded applications will be the intensive data transfer and storage and the need for efficient memory management. The embedded system designer community needs optimization methodologies and techniques, which do not change the input-output functionality of the software applications or the design of the underlying hardware platform. In this paper, the key focus is the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the data memory hierarchy of an MPSoC platform. We propose a design tool framework to efficiently automate the time-consuming optimizations for parallelization and memory mapping of static and dynamic data for MPSoCs.
Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor
DAC1