Emerging devices are widely selected for the design of higher density memories and for the exploration of hardware implementations of low-power artificial neural networks. In particular, a Resistive Random Access Memory (RRAM) device is highly immune to cosmic radiation, to have high endurance and retention. Moreover, its internal structure is quite simple which makes it compatible with mature CMOS processes. However, the device-to-device variability and probabilistic switching are its Achilles’ heel. In this paper a circuit for fine-tuning of RRAM’s resistance is proposed based on the injection of current pulses at SET. A compact model which includes the variability effects is selected and calibrated with a real RRAM and is included in a 65 nm CMOS process to evaluate the proposal. Two tuning modes are obtained: discrete and continuous programming. In the discrete mode, predetermined levels of the resistance can be set up, storing up to 4 bits in a single RRAM in the most favorable case. In the continuous mode, the resistance can be gradually modified in finer steps, but the achieved resistance level is unknown and must be measured.

In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/pFinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the layout area of the eDRAM cells (>10%).

Environmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity to environmental fluctuations yields to a wider range of possible time deviations, being for example, in an NOT gate designed in a 16 nm technology 1.6 times larger than for a 45 nm version. But this ratio is different for every circuit cause it depends on its fundamental structure and characteristics. In this paper the tendency of timing parameters deviations due to environmental factors fluctuation and how these deviations have deeper impact on more complex structures are analyzed. It is shown that the internal structure of the logic gates cause a mismatch between logic circuits and in future technologies it will be enlarged.

In this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage to require information well known by designer, simple and easy to apply even for complex circuits. With only the knowledge of the input signal spectrum and the transfer function from the input to the circuit nodes allows an efficient estimation of the correlation coefficients. A model for computing transition activity in terms only of spectral distribution is also developed. The spectral analysis gives new criteria to obtain power optimization. Experimental results validating the method are also included in this paper