Ishfaq Hussain

dblp:190/1549 · DBLP profile ↗
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4ranked-venue papers
4as first author
3since 2021 · last 2022
0000-0002-4470-1744ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 first-author · 1 since 2021
YearPublicationVenuePosition
2022 Schedulability analysis for CAN bus messages of periodically-varying size
abstract
Conventional CAN bus schedulability analysis as-sumes that all messages with a given identifier have the same worst-case length. In this paper we extend that analysis to a more general model in which messages with a given identifier may have different lengths, that vary according to a known periodic pattern. That is, for some positive integer$s$, we assume that the length of message instances$n$and$n+S$with the same id is the same. By leveraging such patterns, where present, our new analysis allows for a more efficient use of CAN bus bandwidth than the application of conventional analysis, which can be pessimistic. This may be interesting when a given node sends the values of multiple signals with different periods. In such a scenario, the conventional CAN schedulability analysis would require either the use of different ids for different signals (assuming there are enough of them), which leads to a higher bandwidth overhead because of the reduplication of message headers, or using only one id, but pessimistically always assuming the maximum possible length of the message, for safety reasons.
Ishfaq Hussain, Pedro F. Souto, Konstantinos Bletsas 0001, Muhammad Ali Awan, Eduardo Tovar
WFCS1
2022 Response time analysis of memory-bandwidth-regulated multiframe mixed-criticality systems
Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas 0001, Eduardo Tovar
J. Syst. Archit.1
2021 Response time analysis of multiframe mixed-criticality systems with arbitrary deadlines
Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas 0001, Benny Akesson, Eduardo Tovar
Real Time Syst.1
2017 NSGA-II-Based Design Space Exploration for Energy and Throughput Aware Multicore Architectures
abstract
Multicore architectures are mainstream due to ever increasing demand of throughput by modern applications. However, the suboptimal utilization of available resources in these architectures may imply an inevitable energy overhead. This energy overhead can only be avoided if the multicore systems support reconfiguration of available resources as per application demand. To achieve the target objectives (i.e., Energy efficiency with Throughput maximization) in multicore systems, many decision variables need to be optimized or analyzed to find the better trade-off. Heuristic-based approaches are aimed to provide a good-enough solution instead of a lengthy exhaustive search. This paper presents an Evolutionary Algorithm (EA)-based approach, i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II). Three decision variables, i.e., number of cores, cache size and frequency are used to find best solution. The proposed approach is validated over a set of parallel benchmarks using a cycle accurate simulator. The results show a significant amount of energy saving along with minimal impact on the throughput of the system.
Ishfaq Hussain, Abida Parveen, Ayaz Ahmad, Muhammad Yasir Qadri, Nadia N. Qadri, Jameel Ahmed
Cybern. Syst.1