Demo Data from EDBT 2026 / reviewers in the wild / expert
Kohei Matsuda
dblp:190/1876
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2020
0000-0001-7713-4419ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 2Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% | |
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design › cryptographic hardware
AES encryption engine |
0.4 | 1 | 2020 | High Throughput/Gate AES Hardware Architectures Based on Datapath Compression · IEEE Trans. Computers 2020 |
Integrated circuit design › digital circuit design
cryptographic hardware |
0.4 | 1 | 2020 | High Throughput/Gate AES Hardware Architectures Based on Datapath Compression · IEEE Trans. Computers 2020 |
Integrated circuit design
low-power circuit design |
0.4 | 1 | 2020 | High Throughput/Gate AES Hardware Architectures Based on Datapath Compression · IEEE Trans. Computers 2020 |
Cryptographic primitives and cryptanalysis › block cipher
AES |
0.1 | 1 | 2020 | High Throughput/Gate AES Hardware Architectures Based on Datapath Compression · IEEE Trans. Computers 2020 |
Cryptographic primitives and cryptanalysis
block cipher |
0.1 | 1 | 2020 | High Throughput/Gate AES Hardware Architectures Based on Datapath Compression · IEEE Trans. Computers 2020 |
Methods — techniques the papers use, named apart from their topics
logic synthesis · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | High Throughput/Gate AES Hardware Architectures Based on Datapath CompressionabstractThis article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts. Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger |
IEEE Trans. Computers | 5 |
| 2019 | Side-Channel Leakage of Alarm Signal for a Bulk-Current-Based Laser Sensor
Yang Li 0001, Ryota Hatano, Sho Tada, Kohei Matsuda, Noriyuki Miura, Takeshi Sugawara 0001, Kazuo Sakiyama |
Inscrypt | 4 |
| 2017 | Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault AnalysisabstractMatsuda et al. proposed a countermeasure against laser fault injection that uses distributed on-chip sensors. The sensor raises an alarm by detecting an electrical phenomenon caused in conjunction with a bitflip. A cryptographic module can stop releasing a faulty ciphertext by using the alarm. In this paper, security and limitation of the countermeasure by Matsuda et al. is rigorously evaluated. We show that an attacker can get side-channel information by observing how the sensors react to laser fault injection. That enables the attacker to probe intermediate values in a chip non-invasively. On the one hand, under a chosen-plaintext setting, the laser-based probing enables to run the conventional probing attack on AES by Schmidt and Kim. On the other hand, under a ciphertext-only setting, the laser-based probing raises a new challenge: the attacker is given correct ciphertexts and corresponding single-bit probing results. We propose a new ineffective fault analysis against AES based on linear cryptanalysis that can be used in the above setting. Takeshi Sugawara 0001, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata |
FDTC | 4 |