Demo Data from EDBT 2026 / reviewers in the wild / expert
Jea Woo Park
dblp:190/3364
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2018
0000-0002-7143-4418ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.6 | 2 | 2018 | Litho-Aware Machine Learning for Hotspot Detection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Electronic design automation › design for manufacturability
lithography-aware design |
0.3 | 1 | 2018 | Litho-Aware Machine Learning for Hotspot Detection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › physical design › lithography
lithography hotspot detection |
0.3 | 1 | 2018 | Litho-Aware Machine Learning for Hotspot Detection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › physical design › layout verification
design rule checking |
0.2 | 1 | 2016 | Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Electronic design automation › hardware verification and test
pattern matching |
0.2 | 1 | 2016 | Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Methods — techniques the papers use, named apart from their topics
support vector machine · 0.3latent image intensity sampling · 0.3vector space representation · 0.2rectangle dissection · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Litho-Aware Machine Learning for Hotspot DetectionabstractIn this paper, we propose a novel methodology for machine learning-based hotspot detection that uses lithography information to build support vector machine (SVM) during its learning process. Unlike previous studies that use only geometric information or require a post-optical proximity correction (OPC) mask, this proposed method utilizes detailed optical information but bypasses post-OPC mask by sampling latent image intensity and uses those points to train an SVM model. The results suggest high accuracy and low false alarm, and faster runtime compared with methods that require a post-OPC mask. Jea Woo Park, Andres Torres |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2016 | Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector SpaceabstractIn this paper, we propose novel algorithms for pattern matching which dissects patterns into rectangles based on polygon edges. Unlike other design rule check (DRC)-based pattern matching algorithms, our solution utilizes simple DRC edge length rules to create rectangles for hotspot pattern descriptions. This approach has at least three advantages over other solutions. First, it is faster than other state-of-the-art pattern matching tools. Second, it is intuitive and simple for pattern matching engineers to understand and describe patterns. Third, it scales well for parallel computation. We also show how to improve pattern matching run time using vector space created by an origin rectangle and other reference rectangles inside a pattern bounding box. By adopting the vector concept, we iterate only once or twice when detecting different pattern orientations. Other pattern matching techniques usually iterate eight times (4 rotations × 2 mirrored images) to detect all of the eight different orientations. Our method eliminates these unnecessary iterations. Jea Woo Park, Robert Todd |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |