Mengyao Xie

dblp:190/5112 · DBLP profile ↗
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18ranked-venue papers
3as first author
14since 2021 · last 2026
0000-0002-8511-1118ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 11 · 1 first-author · 9 since 2021Systems, architecture and hardware · 5 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2026 Fuzzing JavaScript JIT Compilers With Optimization Path Feedback
Jiming Wang, Chenggang Wu 0002, Yan Kang 0002, Yuhao Hu, Jikai Ren, Yuanming Lai, Mengyao Xie, Chao Zhang 0008, Tao Li 0022, Zhe Wang 0017
IEEE Trans. Dependable Secur. Comput.8
2025 SyzParam: Incorporating Runtime Parameters into Kernel Driver Fuzzing
abstract
Under the monolithic architecture of the Linux kernel, all its components operate within the same address space. Notably, device drivers constitute over half of the kernel codebase yet are particularly prone to bugs. Therefore, exploring vulnerabilities in drivers is critical for ensuring kernel security. Extensive research has been done to fuzz kernel drivers through system calls and hardware interrupts. Through a comprehensive study of the Linux Kernel Device Model, we identified that the execution of device drivers is also influenced by runtime parameters, including device attributes and kernel module parameters. Our analysis reveals that large portions of the uncovered code are masked by these parameters, which are exposed to the userspace through a specialized virtual file system known as sysfs. Furthermore, adjacent devices interconnected within the same device tree also impact drivers' behavior.
Yan Kang 0002, Chenggang Wu 0002, Kangjie Lu, Jiming Wang, Xingwei Li, Yuhao Hu, Jikai Ren, Yuanming Lai, Mengyao Xie, Zhe Wang 0017
CCS10
2025 Tide: An Efficient Kernel-level Isolation Execution Environment on AArch64 via Dynamically Adjusting Output Address Size
abstract
To enforce the privilege separation in the kernel, kernel-level isolated execution environment (IEE) has become a recent research trend because it can protect critical resources and monitors. Our research found that to isolate the IEE memory, all existing IEEs must act as a reference monitor to isolate page tables and validate their updates, bringing a significant performance overhead. Hence, we propose Tide, a new kernel-level IEE based on the output address size hardware feature on AArch64, which could offload such checks to the hardware. However, it still faces the flexibility and security challenges. To address them, Tide presents using the stage-2 translation to expand the physical address range to flexibly map the IEE memory and perform extra access controls on the physical memory; it designs a novel gate to enter (sneak) into the IEE securely by disabling translation temporarily, and ensures it can only be executed at the fixed locations. The experimental results show that Tide is performant than all existing IEEs on protecting critical kernel structures and security tools.
Shiyang Zhang, Chenggang Wu 0002, Chengxuan Hou, Jinglin Lv, Yinqian Zhang, Yuanming Lai, Mengyao Xie, Yan Kang 0002, Zhe Wang 0017
CCS8
2025 BCFuzz: Bytecode-Driven Fuzzing for JavaScript Engines
abstract
The interpreter and the Just-In-Time (JIT) compiler are two core components of modern JavaScript engines, both of which take bytecodes as input. Most bugs in these components are closely related to specific bytecodes. Therefore, effective fuzzing should pay close attention to how bytecode is generated and exercised. However, previous work fails to consider this aspect and instead focuses primarily on the syntactic and semantic validity of test cases. This causes two major issues: 1) certain bytecodes are never exercised during fuzzing; 2) some bytecodes are exercised infrequently. In this paper, we propose BCFuzz, a bytecode-driven fuzzing approach designed to enhance the diversity of generated bytecode and increase testing opportunities for low-frequency bytecodes. Specifically, we introduce a parser-oriented probing technique to identify the necessary conditions for generating specific bytecodes and use this information to enhance the input generation process. To better test low-frequency bytecodes, we propose bytecode-aware seed preservation, scheduling, and mutation strategies. We evaluate BCFuzz on four mainstream JavaScript engines. In 72 hours of testing, BCFuzz discovers 1.73× and 1.67× more bugs than DIE and Fuzzilli, respectively. In total, BCFuzz uncovered 20 previously unknown bugs. Of these, 17 have already been fixed and one has been assigned a CVE. All the discovered bugs are related to bytecodes.
Jiming Wang, Chenggang Wu 0002, Jikai Ren, Yuhao Hu, Yan Kang 0002, Yuanming Lai, Mengyao Xie, Zhe Wang 0017
ASE8
2025 Shining Light on the Inter-procedural Code Obfuscation: Keep Pace with Progress in Binary Diffing
abstract
Software obfuscation techniques have lost their effectiveness due to the rapid development of binary diffing techniques, which can achieve accurate function matching and identification. In this paper, we propose a new inter-procedural code obfuscation mechanism KHaos , 1 which moves the code across functions to obfuscate the function by using compilation optimizations. Three obfuscation primitives are proposed to separate, aggregate, and hide the function. They can be combined to enhance the obfuscation effect further. This article also reveals distinguishing factors on obfuscation and compiler optimization and presents novel observations to gain insights into the impact of actively utilizing compiler optimization in obfuscation. A prototype of KHaos is implemented and evaluated on a large number of real-world programs. Experimental results show that KHaos outperforms existing code obfuscations and can significantly reduce the accuracy rates of six state-of-the-art binary diffing techniques with lower runtime overhead.
Peihua Zhang, Chenggang Wu 0002, Hanzhi Hu, Lichen Jia, Mingfan Peng, Mengyao Xie, Yuanming Lai, Yan Kang 0002, Zhe Wang 0017
ACM Trans. Archit. Code Optim.7
2024 INS: Identifying and Mitigating Performance Interference in Clouds via Interference-Sensitive Paths
abstract
Identifying and managing performance interference in clouds has long been a critical and challenging task for cloud providers. They keep seeking useful performance indicators from underlying systems to monitor cloud applications accurately. However, state-of-the-art indicators are either sensitive to limited applications and resource contention or are unrobust to the continually changing production environments. There still lacks a practical and efficient indicator for production environments.
Ziwei Huang 0003, Mengyao Xie, Shibo Tang, Zihao Chang, Zhicheng Yao, Yungang Bao, Sa Wang
SoCC2
2024 OptFuzz: Optimization Path Guided Fuzzing for JavaScript JIT Compilers
Jiming Wang, Yan Kang 0002, Chenggang Wu 0002, Yuhao Hu, Jikai Ren, Yuanming Lai, Mengyao Xie, Tao Li 0022, Zhe Wang 0017
USENIX Security Symposium8
2024 HIVE: A Hardware-assisted Isolated Execution Environment for eBPF on AArch64
Peihua Zhang, Chenggang Wu 0002, Yinqian Zhang, Mingfan Peng, Shiyang Zhang, Mengyao Xie, Yuanming Lai, Yan Kang 0002, Zhe Wang 0017
USENIX Security Symposium8
2023 PANIC: PAN-assisted Intra-process Memory Isolation on ARM
abstract
Intra-process memory isolation is a well-known technique to enforce least privilege within a process. In this paper, we propose a generic and efficient intra-process memory isolation technique named PANIC, by leveraging Privileged Access Never (PAN) and load/store unprivileged (LSU) instructions on AArch64. PANIC executes process code in kernel mode and compartments code into trusted and untrusted components. The untrusted code is restricted from accessing the isolated memory region, which is located on user pages, and the trusted code is allowed to access the isolated memory region by using LSU instructions. To mitigate threats induced by running user code in kernel mode, PANIC provides two novel security mechanisms: shim-based memory isolation and sensitive instruction emulation. PANIC provides a generic and efficient isolation primitive that can be applied in three different isolation scenarios: protecting sensitive data in CFI, creating isolated execution environments, and hardening JIT code cache. We have implemented a prototype of PANIC and experimental evaluation shows that PANIC incurs very low performance overhead, and performs better than existing methods.
Mengyao Xie, Chenggang Wu 0002, Yinqian Zhang, Qijing Li, Yuanming Lai, Yan Kang 0002, Wei Wang 0385, Zhe Wang 0017
CCS2
2023 Exploring and Exploiting Uncertainty for Incomplete Multi-View Classification
abstract
Classifying incomplete multi-view data is inevitable since arbitrary view missing widely exists in real-world applications. Although great progress has been achieved, existing incomplete multi-view methods are still difficult to obtain a trustworthy prediction due to the relatively high uncertainty nature of missing views. First, the missing view is of high uncertainty, and thus it is not reasonable to provide a single deterministic imputation. Second, the quality of the imputed data itself is of high uncertainty. To explore and exploit the uncertainty, we propose an Uncertainty-induced Incomplete Multi-View Data Classification (UIMC) model to classify the incomplete multi-view data under a stable and reliable framework. We construct a distribution and sample multiple times to characterize the uncertainty of missing views, and adaptively utilize them according to the sampling quality. Accordingly, the proposed method realizes more perceivable imputation and controllable fusion. Specifically, we model each missing data with a distribution conditioning on the available views and thus introducing uncertainty. Then an evidence-based fusion strategy is employed to guarantee the trustworthy integration of the imputed views. Extensive experiments are conducted on multiple benchmark data sets and our method establishes a state-of-the-art performance in terms of both performance and trustworthiness.
Mengyao Xie, Zongbo Han, Changqing Zhang 0002, Yichen Bai, Qinghua Hu
CVPR1
2023 SpecWands: An Efficient Priority-Based Scheduler Against Speculation Contention Attacks
abstract
Transient execution attacks (TEAs) have gradually become a major security threat to modern high-performance processors. They exploit the vulnerability of speculative execution to illegally access private data, and transmit them through timing-based covert channels. While new vulnerabilities are discovered continuously, the covert channels can be categorized to two types: 1) Persistent Type, in which covert channels are based on the layout changes of buffering, e.g., through caches or TLBs and 2) Volatile Type, in which covert channels are based on the contention of sharing resources, e.g., through execution units or issuing ports. The defenses against the persistent-type covert channels have been well addressed, while those for the volatile-type are still rather inadequate. Existing mitigation schemes for the volatile type such as Speculative Compression and Time-Division-Multiplexing will introduce significant overhead due to the need to stall the pipeline or to disallow resource sharing. In this article, we look into such attacks and defenses with a new perspective, and propose a scheduling-based mitigation scheme, called SpecWands. It consists of three priority-based scheduling policies to prevent an attacker from transmitting the secret in different contention situations. SpecWands not only can defend against both interthread and intrathread-based attacks but also can keep most of the performance benefit from speculative execution and resource-sharing. We evaluate its runtime overhead on SPEC 2017 benchmarks and realistic programs. The experimental results show that SpecWands has a significant performance advantage over the other two representative schemes.
Bowen Tang 0001, Chenggang Wu 0002, Pen-Chung Yew, Yinqian Zhang, Mengyao Xie, Yuanming Lai, Yan Kang 0002, Wei Wang 0385, Zhe Wang 0017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2023 Dancing With Wolves: An Intra-Process Isolation Technique With Privileged Hardware
abstract
Intra-process memory isolation is a cornerstone technique of protecting the sensitive data in memory-corruption defenses, such as the shadow stack in control flow integrity (CFI) and the safe region in code pointer integrity (CPI). In this article, we proposeSEIMI, a highly efficient intra-process memory isolation technique for memory-corruption defenses. The core is to use the efficientSupervisor-mode Access Prevention (SMAP), a hardware feature that is originally used for preventing the kernel from accessing the user space, to achieve intra-process memory isolation. To leverage SMAP,SEIMIcreatively executes the user code in the privileged mode. In addition to enabling the new design of the SMAP-based memory isolation, we further develop multiple new techniques to ensure secure escalation of user code. Extensive experiments show thatSEIMIoutperforms existing isolation mechanisms, including theMemory Protection Keys(MPK) based scheme and theMemory Protection Extensions(MPX) based scheme.
Chenggang Wu 0002, Mengyao Xie, Zhe Wang 0017, Yinqian Zhang, Kangjie Lu, Yuanming Lai, Yan Kang 0002, Min Yang 0002, Tao Li 0022
IEEE Trans. Dependable Secur. Comput.2
2022 CETIS: Retrofitting Intel CET for Generic and Efficient Intra-process Memory Isolation
abstract
Intel control-flow enforcement technology (CET) is a new hardware feature available in recent Intel processors. It supports the coarse-grained control-flow integrity for software to defeat memory corruption attacks. In this paper, we retrofit CET, particularly the write-protected shadow pages of CET used for implementing shadow stacks, to develop a generic and efficient intra-process memory isolation mechanism, dubbed CETIS.
Mengyao Xie, Chenggang Wu 0002, Yinqian Zhang, Yuanming Lai, Yan Kang 0002, Wei Wang 0385, Zhe Wang 0017
CCS1
2022 Making Information Hiding Effective Again
abstract
Information hiding (IH) is an important building block for many defenses against code reuse attacks, such as code-pointer integrity (CPI), control-flow integrity (CFI) and fine-grained code (re-)randomization, because of its effectiveness and performance. It employs randomization to probabilistically “hide” sensitive memory areas, called safe areas, from attackers and ensures their addresses are not leaked by any pointers directly. These defenses used safe areas to protect their critical data, such as jump targets and randomization secrets. However, recent works have shown that IH is vulnerable to various attacks. In this article, we propose a new IH technique called SafeHidden. It continuously re-randomizes the locations of safe areas and thus prevents the attackers from probing and inferring the memory layout to find its location. A new thread-private memory mechanism is proposed to isolate the thread-local safe areas and prevent adversaries from reducing the randomization entropy. It also randomizes the safe areas after the TLB misses to prevent attackers from inferring the address of safe areas using cache side-channels. Existing IH-based defenses can utilize SafeHidden directly without any change. Our experiments show that SafeHidden not only prevents existing attacks effectively but also incurs low performance overhead.
Zhe Wang 0017, Chenggang Wu 0002, Yinqian Zhang, Bowen Tang 0001, Pen-Chung Yew, Mengyao Xie, Yuanming Lai, Yan Kang 0002, Yueqiang Cheng, Zhi-Ping Shi 0002
IEEE Trans. Dependable Secur. Comput.6
2020 SEIMI: Efficient and Secure SMAP-Enabled Intra-process Memory Isolation
abstract
Memory-corruption attacks such as code-reuse attacks and data-only attacks have been a key threat to systems security. To counter these threats, researchers have proposed a variety of defenses, including control-flow integrity (CFI), code-pointer integrity (CPI), and code (re-)randomization. All of them, to be effective, require a security primitive—intra-process protection of confidentiality and/or integrity for sensitive data (such as CFI’s shadow stack and CPI’s safe region).In this paper, we propose SEIMI, a highly efficient intra-process memory isolation technique for memory-corruption defenses to protect their sensitive data. The core of SEIMI is to use the efficient Supervisor-mode Access Prevention (SMAP), a hardware feature that is originally used for preventing the kernel from accessing the user space, to achieve intra-process memory isolation. To leverage SMAP, SEIMI creatively executes the user code in the privileged mode. In addition to enabling the new design of the SMAP-based memory isolation, we further develop multiple new techniques to ensure secure escalation of user code, e.g., using the descriptor caches to capture the potential segment operations and configuring the Virtual Machine Control Structure (VMCS) to invalidate the execution result of the control registers related operations. Extensive experimental results show that SEIMI outperforms existing isolation mechanisms, including both the Memory Protection Keys (MPK) based scheme and the Memory Protection Extensions (MPX) based scheme, while providing secure memory isolation.
Zhe Wang 0017, Chenggang Wu 0002, Mengyao Xie, Yinqian Zhang, Kangjie Lu, Yuanming Lai, Yan Kang 0002, Min Yang 0002
SP3
2019 SafeHidden: An Efficient and Secure Information Hiding Technique Using Re-randomization
Zhe Wang 0017, Chenggang Wu 0002, Yinqian Zhang, Bowen Tang 0001, Pen-Chung Yew, Mengyao Xie, Yuanming Lai, Yan Kang 0002, Yueqiang Cheng, Zhi-Ping Shi 0002
USENIX Security Symposium6
2017 SysMon: Monitoring Memory Behaviors via OS Approach
Mengyao Xie, Lei Liu 0030, Chenggang Wu 0002, Hongna Geng
APPT1
2016 Memos: A full hierarchy hybrid memory management framework
abstract
In this paper, we introduce memos, which integrates suitable memory management policies and schedules resources over the entire memory hierarchy in hybrid memory system. Powered by an OS kernel level monitoring tool, memos captures memory patterns online, and then leverages them to guide the memory page placement and data mapping. Experimental results show, on average, memos can benefit memory utilization, contributing to system throughput and QoS by 19.1% and 23.6%. Moreover, memos can reduce the NVM side memory latency by 3∼83.3%, energy consumption by 25.1∼99%, and benefit the NVM lifetime significantly (40× improvement on average).
Lei Liu 0030, Mengyao Xie, Chenggang Wu 0002
ICCD4