Synchronous Dataflow Graphs (SDFGs) are widely employed to model real-time embedded systems and streaming data processing, where throughput serves as a critical measure of computational efficiency. Parametric Shortest Path (PSP) algorithms offer an effective means of analyzing the optimal throughput of Homogeneous SDFGs (HSDFGs). However, applying PSP algorithms to general SDFGs typically requires a conversion to HSDFGs, which introduces additional overhead in graph transformation and may result in exponential growth in graph size. This paper proposes an extension to a traditional PSP algorithm, enabling direct throughput analysis of SDFGs without explicit conversion to HSDFGs. Furthermore, a graph size reduction technique is incorporated to further optimize the runtime of the proposed algorithm. Experimental results demonstrate that the proposed algorithm achieves, on average, a shorter runtime than three state-of-the-art algorithms. The advantage of the proposed algorithm scales with the size of the SDFG, achieving a speedup of up to 39.05x over the fastest of the three baseline algorithms.

Amidst the prevailing trend of escalating demands for data and computational resources, the efficiency of data utilization emerges as a critical lever for enhancing the performance of deep learning models, especially in the realm of image restoration tasks. This investigation delves into the intricacies of data efficiency in the context of image restoration, with Gaussian image denoising serving as a case study. We postulate a strong correlation between the model's performance and the content information encapsulated in the training images. This hypothesis is rigorously tested through experiments conducted on synthetically blurred datasets. Building on this premise, we delve into the data efficiency within training datasets and introduce an effective and stabilized method for quantifying content information, thereby enabling the ranking of training images based on their influence. Our in-depth analysis sheds light on the impact of various subset selection strategies, informed by this ranking, on model performance. Furthermore, we examine the transferability of these efficient subsets across disparate network architectures. The findings underscore the potential to achieve comparable, if not superior, performance with a fraction of the data-highlighting instances where training IRCNN and Restormer models with only 3.89% and 2.30% of the data resulted in a negligible drop and, in some cases, a slight improvement in PSNR. This investigation offers valuable insights and methodologies to address data efficiency challenges in Gaussian denoising. Similarly, our method yields comparable conclusions in other restoration tasks. We believe this will be beneficial for future research.

Synchronous Dataflow graphs (SDFGs) are widely used to model streaming applications that exhibit data-driven and iterative execution patterns. Graph conversion techniques such as retiming, unfolding, and pipelining are commonly used to optimize the iteration periods (IPs) of SDFGs. In this paper, we propose an extension of the graph conversion based pipelining approach for single-rate SDFGs to multi-rate SDFGs. A new perspective on pipelining is introduced, where the pipelining of a general-time SDFG can be viewed as the retiming of a unit-time SDFG. Based on this perspective, we prove that optimal pipelining can always achieve an IP less than 1 time unit longer than the optimal IP for an SDFG. Furthermore, an efficient optimal SDFG pipelining algorithm called GCP-SDFG is presented. Experimental results show that GCP-SDFG has significant advantages in IP minimizing and runtime relative to three state-of-the-art retiming or pipelining algorithms.

With the development of deep learning, Dynamic Portfolio Optimization (DPO) problem has received a lot of attention in recent years, not only in the field of finance but also in the field of deep learning. Some advanced research in recent years has proposed the application of Deep Reinforcement Learning (DRL) to the DPO problem, which demonstrated to be more advantageous than supervised learning in solving the DPO problem. However, there are still certain unsolved issues: 1) DRL algorithms usually have the problems of slow learning speed and high sample complexity, which is especially problematic when dealing with complex financial data. 2) researchers use DRL simply for the purpose of obtaining high returns, but pay little attention to the problem of risk control and trading strategy, which will affect the stability of model returns. In order to address these issues, in this study we revamped the intrinsic structure of the model based on the Deep Deterministic Policy Gradient (DDPG) and proposed the Augmented DDPG model. Besides, we also proposed an innovative risk control strategy based on Quantum Price Levels (QPLs) derived from Quantum Finance Theory (QFT). Our experimental results revealed that our model has better profitability as well as risk control ability with less sample complexity in the DPO problem compared to the baseline models.

Synchronous dataflow graphs are widely used to model digital signal processing and multimedia applications. Self-timed execution is an efficient methodology for the analysis and scheduling of synchronous dataflow graphs. In this article, we propose a communication-aware self-timed execution approach to solve the problem of scheduling synchronous dataflow graphs on multicore systems with communication delays. Based on this communication-aware self-timed execution approach, four communication-aware scheduling algorithms are proposed using different allocation rules. Furthermore, a code-size-aware mapping heuristic is proposed and jointly used with a proposed scheduling algorithm to reduce the code size of SDFGs on multicore systems. The proposed scheduling algorithms are experimentally evaluated and found to perform better than existing algorithms in terms of throughput and runtime for several applications. The experiments also show that the proposed code-size-aware mapping approach can achieve significant code size reduction with limited throughput degradation in most cases.

Bus routes are typically updated every 3-5 years to meet constantly changing travel demands. However, identifying deficient bus routes and finding their optimal replacements remain challenging due to the difficulties in analyzing a complex bus network and the large solution space comprising alternative routes. Most of the automated approaches cannot produce satisfactory results in real-world settings without laborious inspection and evaluation of the candidates. The limitations observed in these approaches motivate us to collaborate with domain experts and propose a visual analytics solution for the performance analysis and incremental planning of bus routes based on an existing bus network. Developing such a solution involves three major challenges, namely, a) the in-depth analysis of complex bus route networks, b) the interactive generation of improved route candidates, and c) the effective evaluation of alternative bus routes. For challenge a, we employ an overview-to-detail approach by dividing the analysis of a complex bus network into three levels to facilitate the efficient identification of deficient routes. For challenge b, we improve a route generation model and interpret the performance of the generation with tailored visualizations. For challenge c, we incorporate a conflict resolution strategy in the progressive decision-making process to assist users in evaluating the alternative routes and finding the most optimal one. The proposed system is evaluated with two usage scenarios based on real-world data and received positive feedback from the experts. Index Terms-Bus route planning, spatial decision-making, urban data visual analytics.

Synchronous Dataflow Graphs (SDFGs) are widely used to model streaming applications (e.g. digital signal processing applications), which are commonly executed by embedded systems. The usage of on-chip resources is always strictly constrained in embedded systems. As the cost of instruction memory is a significant part of on-chip resource costs, code size reduction is an effective way to control the overall costs of on-chip resources. In this work, a code-size-aware mapping heuristic is proposed to decrease the code size for SDFGs on multicore systems. The mapping heuristic is jointly used with a self-timed scheduling heuristic to decrease the code size of the original schedule. In preliminary experiments, the proposed heuristic achieves significant code size reduction for all the tested SDFGs without affecting throughput.