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Fulin Peng

dblp:190/7511 · DBLP profile ↗
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3ranked-venue papers
2as first author
1since 2021 · last 2024
0000-0003-2187-8296ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 84% Hardware reliability and fault tolerance · 16%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.412020
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › yield analysis
rare failure analysis
0.412020
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Hardware reliability and fault tolerance
soft errors
0.412020
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › timing analysis
statistical timing analysis
0.412020
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation
design optimization
0.312018
A general graph based pessimism reduction framework for design optimization of timing closure · DAC 2018
Electronic design automation
timing analysis
0.312018
A general graph based pessimism reduction framework for design optimization of timing closure · DAC 2018
Electronic design automation › physical design
timing optimization
0.312018
A general graph based pessimism reduction framework for design optimization of timing closure · DAC 2018

Methods — techniques the papers use, named apart from their topics

hierarchical subset simulation · 0.4asymptotic probability approximation · 0.4stochastic conjugate gradient · 0.3quadratic programming · 0.3critical path selection · 0.3
YearPublicationVenuePosition
2024 Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation
abstract
The reliability of circuits is significantly affected by process variations in manufacturing and environmental variation during operation. Current yield optimization algorithms take process variations into consideration to improve circuit reliability. However, the influence of environmental variations (e.g., voltage and temperature variations) is often ignored in current methods because of the high computational cost. In this article, a novel and efficient approach named BNN-BYO is proposed to optimize the yield of analog circuits in multiple environmental corners. First, we use a Bayesian Neural Network (BNN) to simultaneously model the yields and performances of interest in multiple corners efficiently. Next, the multi-corner yield optimization can be performed by embedding BNN into a Bayesian optimization framework. Since the correlation among yields and performances of interest in different corners is implicitly encoded in the BNN model, it provides great modeling capabilities for yields and their uncertainties to improve the efficiency of yield optimization. Our experimental results demonstrate that the proposed method can save up to 45.3% of simulation cost compared to other baseline methods to achieve the same target yield. In addition, for the same simulation cost, our proposed method can find better design points with 3.2% yield improvement.
Nanlin Guo, Fulin Peng, Jiahe Shi, Fan Yang 0001, Jun Tao 0001, Xuan Zeng 0001
ACM Trans. Design Autom. Electr. Syst.2
2020 Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation
abstract
In this article, a novel asymptotic probability approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key idea of APA is to approximate the overall circuit failure rate based on a set of carefully defined failure events. An efficient hierarchical subset simulation (H-SUS) method is developed to calculate the aforementioned failure rate and a statistical methodology is further proposed to estimate the confidence interval of APA. Our numerical experiments demonstrate that APA can accurately and reliably estimate the overall failure rate of correlated rare failure events involving more than 20 000 independent random variables.
Fulin Peng, Handi Yu, Jun Tao 0001, Yangfeng Su, Dian Zhou, Xuan Zeng 0001, Xin Li 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2018 A general graph based pessimism reduction framework for design optimization of timing closure
abstract
In this paper, we develop a general pessimism reduction framework for design optimization of timing closure. Although the modified graph based timing analysis (mGBA) slack model can be readily formulated into a quadratic programming problem with constraints, the realistic difficulty is the size of the problem. A critical path selection scheme, a uniform sampling method with the sparse characteristics of the optimal solution, and a stochastic conjugate gradient method are proposed to accelerate the optimization solver. This modified GBA is embedded into design optimization of timing closure. Experimental results show that the proposed solver can achieve 13.82x speedup than gradient descent method with similar accuracy. With mGBA, the optimization of timing closure can achieve a better performance on area, leakage power, buffer counts.
Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng 0001
DAC1