In this work, a novel signal processing approach for the efficient computation of the cross-correlation operator on low-complexity FPGAs is presented. Sets-Of-Real-Numbers (SORNs) arithmetic is exploited to build resource-efficient multipliers that are carefully injected into the hardware architecture. By this measure, a significant decrease of arithmetic hardware requirements is achieved. Especially, in the scope of low-complexity FPGAs, this depicts an enormous advantage, as these devices usually only have a few or even no specific arithmetic hardware accelerators, such as DSP blocks, at all. In order to smoothly integrate these special multipliers, additional conversion functions are needed to handle the number format transformation between SORNs and the fixed-point (FxD) data representation. For the evaluation, several cross-correlation-related hardware architectures with different number formats, data types, and multipliers are taken into account. Out of this, the proposed SORN-based implementation turns out to achieve extremely high performance regarding the resulting signal quality. In terms of the resource utilization, it clearly outperforms the traditional FxD-based architectures. Hence, SORN-based multipliers identify as a powerful extension for calculating the cross-correlation on low-complexity FPGAs.

SORN Arithmetic is a low-complexity and low-precision digital number format based on intervals that can be useful for preprocessing large datasets. Since the interval width of a SORN result is likely to grow with the number of operations, the concept of fused SORN operations is proposed. Functions with more than one operation are evaluated without intermediate quantization, reducing spurious interval growth (the “dependency problem”) and increasing the resulting precision. The presented evaluations for basic and complex fused functions show a reduction of the output interval widths of up to 53%. In addition, introducing fused SORN operations also leads to significant hardware reductions in area, power consumption and path delay. Compared to the non-fused designs, reductions of the Area-Power-Timing-product of up to 88% can be achieved.

Sets-Of-Real-Numbers (SORN) Arithmetic derives from the Unum type-II number format and provides high throughput and low complexity computations at the cost of a very rough resolution. This work presents a symbol detection unit for MIMO transmission with a BPSK modulation which consists of a SORN preprocessor applying an exhaustive search method and a fixed-point module processing the results from the SORN unit. Different SORN datatypes and hardware configurations are considered and evaluated throughout BER simulations and postsynthesis analyses.

In this paper different SORN (Sets Of Real Numbers) datatype configurations are analyzed for unum type-2-based arithmetic applied to symbol detection in a wireless MIMO communication system. Different SORN interval properties and MIMO-specific performance measures as well as the corresponding hardware architectures are evaluated in order to rate the suitability of the different configurations for the target application. The evaluation of the proposed datatypes indicates an improvement in the solution set reduction of up to 95.4 % and a hardware complexity reduction of 30.3 % comparing the proposed 17 bit configuration to the original unum type-2-based 16 bit SORNs.

This article provides an efficient hardware generator for high-performance sets-of-real-numbers (SORNs) arithmetic. Complex datapaths are automatically built in VHDL, comprising the generation of arithmetic operations and functions as well as all necessary interconnects. Various SORN datatypes can be easily set up enabling high adaptivity to different applications. For further performance improvements additional optimization and implementation techniques are considered as well. For evaluation, a SORN-based symbol detector for a multiantenna wireless communication scenario is generated that solves a system of linear equations. As SORN-based signal processing allows a quick but rough calculation of the system equations outcome, it can be exploited to reject possible input vectors that do not satisfy the general constraints of the signal detection task. Hence, this generally leads to a heavily reduced set of remaining solutions. Multiple hardware architectures with different SORN datatypes are generated and compared. Further, an analysis is performed considering the signal-to-noise ratio (SNR). Finally, logic synthesis is applied to selected designs and compared to references from the literature highlighting this article to be highly hardware-efficient and suitable for application-specific signal processing.