The ever increasing technological demand for the DFT computation poses several challenges both to theory and hardware realization. The design of usual fast Fourier transform (FFT) algorithms seems to have reached a stage of diminishing returns in terms of performance. Alternatively, approximate transform methods have been demonstrated to provide substantial gains in terms of energy-efficiency and performance by tolerating small inaccuracies in the results. In this paper, we present a transform scaling method variant of the Cooley-Tukey algorithm to obtain DFT approximations of large blocksize. The proposed method scales up a givenN-point transformation to anN2-point transformation. Such scaling can be successively applied leading to$\mathop {{N}^2}\nolimits^n $-point transformations. We have fully presented the 324-point DFT approximation which stems from a multiplierless 32-point DFT approximation. The proposed approximation is equipped with a fast algorithm; we also supply the arithmetic complexity assessment and an error analysis.

The discrete cosine transform (DCT) is a relevant tool in signal processing applications, mainly known for its good decorrelation properties. Current image and video coding standards—such as JPEG and HEVC—adopt the DCT as a fundamental building block for compression. Recent works have introduced low-complexity approximations for the DCT, which become paramount in applications demanding real-time computation and low-power consumption. The design of DCT approximations involves a trade-off between computational complexity and performance. This paper introduces a new multiparametric transform class encompassing the round-off DCT (RDCT) and the modified RDCT (MRDCT), two relevant multiplierless 8-point approximate DCTs. The associated fast algorithm is provided. Four novel orthogonal low-complexity 8-point DCT approximations are obtained by solving a multicriteria optimization problem. The optimal 8-point transforms are scaled to lengths 16 and 32 while keeping the arithmetic complexity low. The proposed methods are assessed by proximity and coding measures with respect to the exact DCT. Image and video coding experiments and hardware realization are performed. The novel transforms perform close to or outperform the current state-of-the-art DCT approximations.

This paper proposes a computational method for 2D 8×8 DCT based on algebraic integers. The proposed algorithm is based on the Loeffler 1D DCT algorithm, and it is shown to operate with exact computation—i.e., error-free arithmetic—up to the final reconstruction step (FRS). The proposed algebraic integer architecture maintains error-free computations until an entire block of DCT coefficients having size 8×8 is computed, unlike algorithms in the literature which claim to be error-free but in fact introduce arithmetic errors between the column- and row-wise 1D DCT stages in a 2D DCT operation. Fast algorithms are proposed for the final reconstruction step employing two approaches, namely, the expansion factor and dyadic approximation. A digital architecture is also proposed for a particular FRS algorithm, and is implemented on an FPGA platform for on-chip verification. The FPGA implementation operates at 360 MHz, and is capable of a real-time throughput of$3.6\cdot 10^8$2D DCTs of size 8×8 every second, with corresponding pixel rate of$2.3\cdot 10^{10}$pixels per second. The digital architecture is synthesized using 180 nm CMOS standard cells and shows a chip area of 7.41 mm$^2$. The CMOS design is predicted to operate at 893 MHz clock frequency, at a dynamic power consumption 13.22 mW/MHz$\cdot$V$_{sup}^2$.

This paper introduces a new method for computing matrix exponential based on truncated Neumann series. The efficiency of the method is based on smart factorizations for evaluation of several Neumann series that can be done in parallel and divided across different processors with low communication overhead. A physical realization on FPGA is provided for proof-of-concept. The method is verified to be advantageous over the usual Horner's rule approach for polynomial evaluation. The hardware verification shows a reduction of 62% in time required for processing for series approximations with 9 terms. Software verification demonstrates a 30% reduction in time compared to Horner's rule and the trade-offs between using a higher precision approach is illustrated.

A joint numerical representation based on both Gaussian and Eisenstein integers is proposed. This Gauss-Eisenstein representation maps complex numbers into four-tuples of integers with arbitrarily high precision. The representation furnishes the computation of the 3-, 6-, and 12-point discrete Fourier transform (DFT) at any desired accuracy. The associated fast algorithms based on the Gauss-Eisenstein integers are error-free up to the final reconstruction step, which can be realized in hardware as a multiplierless implementation. The introduced methods are compared with competing algorithms in terms of arithmetic complexity. We propose three FRS architectures based on the following methods: Dempster-McLeod representation, expansion factor, and addition aware quantization. The Gauss-Eisenstein 12-point DFT is physically realized on a Xilinx Virtex 6 FPGA device with maximum clock frequency of 302 MHz for the expansion factor FRS with real-time throughput of 3:62 × 109 coefficients/s. The FPGA verified digital designs were synthesized, mapped, placed and finally routed for 0:18mm CMOS technology assuming a 1.8 V DC supply employing Austria Micro Systems (AMS) standard-cell library (hitkit version 4.11). The routed ASIC is predicted to operate at a maximum frequency of 505 MHz for the expansion factor FRS with potential real-time throughput of 6:06 × 109coefficients/s.

An 8‐point discrete cosine transform (DCT) fast algorithm based on the Loeffler DCT factorisation and algebraic integer (AI) representation is proposed. The proposed algorithm is an error‐free implementation of the Loeffler algorithm and it is capable of computing the 8‐point DCT multiplierlessly. Decoding architectures are also proposed for mapping AI encoded quantities back to usual fixed point arithmetic using canonical signed digit representation and the expansion factor method. The proposed algorithm is mapped into systolic‐array digital architectures and physically realised as digital prototype circuits using field‐programmable gate array technology on a Reconfigurable Open Architecture Computing Hardware board and mapped to 0.18 μm complementary metal–oxide–semiconductor technology using AMS Encounter Digital Implementation libraries at 1.8 V supply.