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Artem Y. Polyakov

dblp:191/3084 · DBLP profile ↗
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5ranked-venue papers
2as first author
2since 2021 · last 2025
0000-0001-6759-1448ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Cloud and datacenter computing · 77% Interconnection networks and networks-on-chip · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing › virtualization
device pass-through
0.912025
Device-Assisted Live Migration of RDMA Devices · SOSP 2025
Cloud and datacenter computing › virtualization › virtual machine migration
live migration
0.912025
Device-Assisted Live Migration of RDMA Devices · SOSP 2025
Interconnection networks and networks-on-chip
remote direct memory access
0.912025
Device-Assisted Live Migration of RDMA Devices · SOSP 2025
Cloud and datacenter computing
virtualization
0.912025
Device-Assisted Live Migration of RDMA Devices · SOSP 2025
Cloud and datacenter computing
cloud infrastructure
0.312025
Device-Assisted Live Migration of RDMA Devices · SOSP 2025
YearPublicationVenuePosition
2025 Device-Assisted Live Migration of RDMA Devices
abstract
Recently, we have seen growing pressure to move highperformance workloads, such as HPC and AI, to cloud environments that offer more affordable and manageable infrastructure. These workloads require direct access to RDMA devices for high-performance communication. Device passthrough, however, violates the decoupling between the guest OS and the underlying hardware, making Live Migration (LM) extremely challenging [29, 38, 40, 42, 48].
Artem Y. Polyakov, Gal Shalom, Asaf Schwartz, Aviad Yehezkel, Omri Ben David, Omri Kahalon, Ariel Shahar, Liran Liss
SOSP1
2024 Message from the General Chairs HOTI 2024
abstract
For more than 30 years, Hot Interconnects (HotI) has been a venue for discussions on cutting-edge network products, innovations in the network ecosystem, and a venue for introducing new network products in both software and hardware. This tradition continues with the 31st edition of the conference and it is reflected in the engaging program we have planned for HotI 2024. This year will be an online-only event and we expect over 1000 participants from all over the world. In addition, we are proud to announce best paper awards to highlight the novel and impactful work that is part of this year's program.
Matthew G. F. Dosanjh, Artem Y. Polyakov
HOTI2
2019 A performance analysis and optimization of PMIx-based HPC software stacks
abstract
Process management libraries and runtime environments serve an important role in the HPC application lifecycle. This work provides a roadmap for implementing a high-performance PMIx based software stacks and targets four performance-critical areas presenting novel codesigned solutions that significantly improve application performance during initialization and wire-up at scale.
Artem Y. Polyakov, Boris I. Karasev, Joshua Hursey, Joshua Ladd, Mikhail Brinskii, Elena Shipunova
EuroMPI1
2016 Design and Implementation for Checkpointing of Distributed Resources Using Process-Level Virtualization
abstract
System-level checkpoint-restart is a critical technology for long-running jobs in high-performance computing. Yet, only two approaches to checkpointing MPI applications continue to survive in wide use today. One approach is to use the kernel module-based BLCR in combination with an MPI checkpoint-restart service particular to the MPI implementation in use. Unfortunately, this lacks support for some important Linux system services such as SysV IPC (e.g., shared memory objects). A second approach has been to use the original 2009 DMTCP implementation (herein referred to as DMTCP-09) for transparent, system-level checkpointing. Unfortunately, DMTCP-09 lacked support for checkpointing many of the necessary features found by MPI in a modern batch environment. These include: ssh, the InfiniBand network, process migration (restarting an MPI application on different cluster nodes), and modified file path prefixes on restart (typically due to a changing current directory, mount points, library paths, etc.). This work presents DMTCP-PV, a new user-space transparent checkpointing system based on the concept of process virtualization. This approach separately models the state of each local or distributed subsystem while decoupling it from the core checkpointing engine. By separating these concerns, a domain expert can extend checkpointing into a new domain without any knowledge of the core checkpointing engine. This allowed DMTCP-PV to address the deficiencies noted above and many others. It is shown that the runtime overhead of DMTCP-PV is generally less than 1%, and the checkpointing time is dominated by the time to write an image file to stable storage.
Kapil Arya, Rohan Garg 0001, Artem Y. Polyakov, Gene Cooperman
CLUSTER3
2016 Using InfiniBand Hardware Gather-Scatter Capabilities to Optimize MPI All-to-All
abstract
The MPI all-to-all algorithm is a data intensive, high-cost collective algorithm used by many scientific High Performance Computing applications. Optimizations for small data exchange use aggregation techniques, such as the Bruck algorithm, to minimize the number of messages sent, and minimize overall operation latency. This paper presents three variants of the Bruck algorithm, which differ in the way data is laid out in memory at intermediate steps of the algorithm. Mellanox's InfiniBand support for Host Channel Adapter (HCA) hardware scatter/gather is used selectively to replace CPU-based buffer packing and unpacking. Using this offload capability reduces the eight and sixteen byte all-to-all latency on 1024 MPI Processes by 9.7% and 9.1%, respectively. The optimization accounts for a decrease in the total memory handling time of 40.6% and 57.9%, respectively.
Ana Gainaru, Richard L. Graham, Artem Y. Polyakov, Gilad Shainer
EuroMPI3