EDBT 2026 Demo / reviewers in the wild / expert
Enrique Díaz
dblp:191/8309
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 44% Electronic design automation · 44% Performance modeling and evaluation · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › timing analysis › real-time timing analysis
multicore timing analysis |
0.3 | 1 | 2018 | Modelling multicore contention on the AURIXTM TC27x · DAC 2018 |
Embedded and real-time systems
worst-case execution time analysis |
0.3 | 1 | 2018 | Modelling multicore contention on the AURIXTM TC27x · DAC 2018 |
Performance modeling and evaluation
performance monitoring |
0.1 | 1 | 2018 | Modelling multicore contention on the AURIXTM TC27x · DAC 2018 |
Methods — techniques the papers use, named apart from their topics
performance counters · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Modelling multicore contention on the AURIXTM TC27xabstractMulticores are becoming ubiquitous in automotive. Yet, the expected benefits on integration are challenged by multicore contention concerns on timing V&V. Worst-case execution time (WCET) estimates are required as early as possible in the software development, to enable prompt detection of timing misbehavior. Factoring in multicore contention necessarily builds on conservative assumptions on interference, independent of co-runners load on shared hardware. We propose a contention model for automotive multicores that balances time-composability with tightness by exploiting available information on contenders. We tailor the model to the AURIX TC27x and provide tight WCET estimates using information from performance monitors and software configurations. Enrique Díaz, Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella 0001, Francisco J. Cazorla |
DAC | 1 |