This article describes a systematic and scalable electrostatic discharge (ESD) verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. The tool identifies the ESD protection network of a circuit thanks to a flexible topology-aware mechanism and converts the circuit description of this network into a directed graph whose edges are provided with quasistatic electrical behaviors inferred from the machine learning techniques detailed in a companion paper. A graph-based analysis establishes a risk rating cartography for all top-level pad-to-pad discharge combinations. The circuit reviewer, a chip designer, or an ESD expert can, therefore, assess the ESD performances of the ESD network under study and easily investigate potential ESD design weaknesses.

This article gives a detailed insight on a machine learning procedure to infer quasistatic quantities of electrostatic discharge (ESD) protection structures from their instance parameters in a netlist. It resorts to a dataset of transmission line pulse (TLP) I-V curves that have been obtained from numerous transient electrical simulations. The tuning of machine learning algorithms and the quantification of their generalized prediction performances on out-of-sample data are performed by means of nested cross-validation. Resulting fitted analytical models are encompassed in a tool called ESD IP Explorer in charge of providing a systematic and scalable ESD verification methodology. This tool, which has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures, is described in a former article.