Power supply noise (PSN) in central processing unit (CPU) cores or any integrated circuit (IC) chips is a problem of power line voltage degradation impelled due to the parasitic components (viz., resistance, capacitance, and inductance) across the packaging. This lowers the operating frequency of the silicon chip during high volume manufacturing and thereby, affects the overall performance. After numerous attempts to minimize the parasitic impacts of power delivery networks (PDNs) in IC packages, researchers also started to look for circuital configurations that can curb down the coefficients of PSN (i.e., the instantaneous current$i(t)$and the current ramp$[({di(t)})/{dt}]$during OFF to ON switching of packaged CPU/IC). Though variable frequency clock (VFC) has emerged as a potential solution, its design is found to be complex and power hungry. Hence, a novel and simple configuration of VFC embedded with leakage control transistor-based clock gating (LCT-CG) is tendered in this article, where the pertaining circuits and integrated system have been designed using UMC 65 nm CMOS with a supply of 1.1 V. The performance of the design is tested on master-slave flip-flop (MSFF) and a few prominent benchmark circuits (viz., ISCAS’89 s27, s820, s832, s1196, s9234 and ITC’99 b02 and an IEEE 754 complaint single precision FPU) considering the PDN of existing CPU OLGA package. The system-level validation of our proposed IC on A-Z80 CPU chip offers the average power and PSN to be mitigated by 30.06% and 42.63% against the conventional clocking.

An algorithm is proposed for segmentation of digital images using the curve fitting method based on modified Vandermonde matrix and modified Gram‐Schmidt method. Modified Vandermonde matrix is applied to linearly smoothed histogram data to find the coefficients of a polynomial of a given degree for fitting the data in a least square sense. Modified Gram‐Schmidt method is applied to get polynomial coefficients to minimise the least square distance during the calculation. The threshold value is computed by locating the minimum number of pixels from the grey‐level value. Threshold value is used with that of the input image to generate an output segmented image. The output segmented image is further improved by applying morphological operation which has made the segmented edge lines and regions free from any extraneous pixels. The final segmented image has been found to have sharp edges and filled in a region within the image contours. The experimental results show that the proposed method has produced superior performance compared to other state‐of‐art algorithms. Further, it is observed from the results that the proposed algorithm takes less program execution time than others in vogue algorithms.

An adaptive plateau limit‐based histogram equalisation algorithm is suggested to enhance digital images. Histogram of the image is clipped with a plateau limit to avoid over enhancement. The plateau limit is derived from the average of the mean and the median intensity values to offer the improved enhancement. Clipped histogram is subdivided into three parts, using histogram subdivision limit parameters that are calculated on the basis of the standard deviation of the image. Histogram of individual sub‐image is equalised independently and then combined into a single enhanced image. Experimental results demonstrate that the proposed plateau limit‐based tri‐histogram equalisation algorithm enhances the image quality. Compared with the other traditional plateau and non‐plateau limit‐based histogram equalisation algorithms, quantitative and visual quality assessments effectively validate the superiority of the proposed algorithm.