Implantable biomedical circuits offer wide applications including the treatment of neurological disorders. To ensure reliability in terms of ESD (Electrostatic discharge) damage from fabrication, packaging, and user handling, ESD protection is required to protect the core circuit from any damage. A complete closed-loop neuromodulation SoC with on-site recording and digital core coupled with the cost necessitates the design to be implemented in a 65nm CMOS technology. Custom ESD protection has to be incorporated since the foundry-provided ESD cannot handle the high voltages required for faithful current stimulations. While existing stimulator designs in 65nm CMOS use implicit diodes of the driver stage as part of ESD protection, we show that this leads to coupling of the ESD design with the driver design, leading to suboptimal area and possible failure cases due to stress. This work proposes a 10 V compliant stimulator with an ESD protection circuit in± a 65 nm CMOS process verified for the HBM model using post-layout TLP simulations. This work also provides insights and details on the decoupling of the ESD design from the stimulator driver design to realize a low-footprint device.

This work proposes a neuromodulation-inspired spiking neural network using a ReRAM memory. A stashing-merging algorithm is realized to mimic the inherent neuromodulation in humans. While traditional pruning methods remove redundant parts of the network, stashing excludes well-trained neurons while training and restores all neurons at the end of training. This approach exhibits energy-efficient training in the context of a spiking neural network (SNN) since well-trained neurons can be easily identified using the spike count. The idea is validated using a ReRAM-based SNN with 10 conductance levels and performs close to a traditional artificial neural network (ANN) on an MNIST classification workload.

Resistive random access memory (ReRAM) based analog in-memory-compute (IMC) coupled with spiking neural networks (SNN) offers a promising solution to implement efficient matrix multiplication. This work presents an ARM Cortex-based ReRAM IMC for rapid SNN workload evaluation. While the software flexibility and the scheduling are provided by the ARM processing system (PS), the programmable logic (PL) provides a scalable interface to the ReRAM array through mixed-signal digital-to-analog converters (DAC). A prototype system is presented using a Zynq 7000 SoC comprising an ARM PS and PL infrastructure. Custom 8x8 ReRAM array along with row and column DACs and leaky-integrate and fire (LIF) neurons are implemented to realize the end-to-end system. A use-case of a stashing-based MNIST classification task is demonstrated using the prototype system.

To enable a dense integration of model synapses in a spiking neural networks (SNN) hardware, various nanoscale devices are being considered. Such devices, besides exhibiting spike-timing dependent plasticity (STDP), need to be highly scalable, have a large endurance and require low energy for transitioning between states. In this work, first, we introduce and empirically determine two new specifications for a resistive random-access memory (RRAM) based synapse: number of conductance levels per synapse and learning-rate. To the best of our knowledge, there are no RRAMs that meet the latter specification. As a solution, we propose the use of multiple RRAMs in parallel within a synapse. While synaptic reading, all RRAMs are simultaneously read and for each synaptic conductance-change event, the mechanism for conductance STDP is initiated on only one RRAM, randomly picked from the set. Second, to validate our solution, we experimentally demonstrate STDP of conductance of a Pr0.7Ca0.3MnO3(PCMO)-RRAM and then show that due to a large learning-rate, a single PCMO-RRAM fails to model a synapse in the training of an SNN. As anticipated, network training improved as more PCMO-RRAMs were added to the synapse. Fourth, we discuss circuit-requirements for implementing such a scheme, to conclude that the requirements are within bounds. Thus, our work presents specifications for synaptic devices in trainable SNNs, indicates the shortcomings of state-of-art synaptic contenders, and provides a solution to extrinsically meet the specifications and discusses the peripheral circuitry that implements the solution.