EDBT 2026 Demo / reviewers in the wild / expert
Mark Sagi
dblp:192/4466
· DBLP profile ↗
3ranked-venue papers
2as first author
1since 2021 · last 2021
0000-0001-7380-3793ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Energy-efficient computing · 64% Parallel and multicore computing · 16% High-performance computing · 16% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing › power management › power budgeting
dynamic power budgeting |
0.4 | 1 | 2020 | Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores · IEEE Trans. Computers 2020 |
High-performance computing
performance optimization |
0.4 | 1 | 2020 | Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores · IEEE Trans. Computers 2020 |
Energy-efficient computing
power management |
0.4 | 1 | 2020 | Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores · IEEE Trans. Computers 2020 |
Energy-efficient computing
power modeling |
0.4 | 1 | 2020 | A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Energy-efficient computing › power modeling
run-time power estimation |
0.4 | 1 | 2020 | A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Parallel and multicore computing
task allocation |
0.4 | 1 | 2020 | Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores · IEEE Trans. Computers 2020 |
Performance modeling and evaluation › performance monitoring
hardware performance counters |
0.1 | 1 | 2020 | A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Methods — techniques the papers use, named apart from their topics
run-time algorithm · 0.4nonlinear transformation · 0.4linear regression · 0.4least angle regression · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core ProcessorsabstractWe propose a novel technique to forecast the power consumption of processor cores at run-time. Power consumption varies strongly with different running applications and within their execution phases. Accurately forecasting future power changes is highly relevant for proactive power/thermal management. While forecasting power is straightforward for known or periodic workloads, the challenge for general unknown workloads at different voltage/frequency (v/n-levels is still unsolved. Our technique is based on a long short-term memory (LSTM) recurrent neural network (RNN) to forecast the average power consumption for both the next 1ms and 10ms periods. The runtime inputs for the LSTM RNN are current and past power information as well as performance counter readings. An LSTM RNN enables this forecasting due to its ability to preserve the history of power and performance counters. Our LSTM RNN needs to be trained only once at design-time while adapting during run-time to different system behavior through its internal memory. We demonstrate that our approach accurately forecasts power for unseen applications at different v/f-levels. The experimental results shows that the forecasts of our LSTM RNN provide 43% lower worst case error for the 1ms forecasts and 38% for the 10ms forecasts. comnared to the state of the art. Mark Sagi, Martin Rapp, Heba Khdr, Yizhe Zhang 0005, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Jörg Henkel, Andreas Herkersdorf |
DATE | 1 |
| 2020 | Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-CoresabstractTwo factors primarily affect the performance of multi-threaded tasks on many-core processors with logically-shared and physically-distributed Last-Level Cache (LLC): the LLC latencies of threads running on different cores and the per-core power budgets that aim to guarantee thermally safe operation. Two knobs affect these factors: First, the mapping of threads to cores affects both the LLC latencies and the power budgets. Second, dynamic power budgeting refines the power budgets during task execution. A mapping that spatially distributes threads across the many-core increases the power budgets, but unfortunately also increases the LLC latencies. Contrarily, mapping all threads near the center of the many-core minimizes the LLC latencies, but unfortunately also decreases the power budgets. Consequently, both metrics cannot be simultaneously optimal, which leads to a Pareto-optimization for task mapping that has formerly not been exploited. Dynamic power budgeting reallocates the power budgets according to the tasks' execution phases. This results in a dynamically changing non-uniform power budget, which further increases the performance. We are the first to present a run-time algorithm PCGov combining task-agnostic task mapping and task-aware dynamic power budgeting for many-cores with shared distributed LLC. PCGov yields up to 21 percent lower response time and 13 percent lower energy consumption compared to the state-of-the-art, with a low overhead of less than 0.5 percent. Martin Rapp, Mark Sagi, Anuj Pathania, Andreas Herkersdorf, Jörg Henkel |
IEEE Trans. Computers | 2 |
| 2020 | A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor PowerabstractMany power management algorithms demand accurate and fine-grained runtime estimations of dynamic core power. In the absence of fine-grained power sensors, model-based estimations are needed. Such power models commonly approximate the switching activity of logic gates using performance counters while assuming a linear performance counter/power relation at a fixed frequency and voltage. It has been shown that this relation cannot be captured accurately enough with purely linear models and that well-established nonlinear modeling techniques, e.g., polynomial modeling, easily overfit the underlying performance/power relations. Although neural-network-based modeling has shown to accurately capture nonlinear relations, it has a large training and inference overhead which is too high for fine-grained models on core-level and estimation rates in the range of 1-10 kHz. We propose a methodology for nonlinear transformation of specific performance counters to increase power modeling accuracy at constant frequency and voltage with a relatively low overhead for both model generation and run-time application over a linear model. Furthermore, we use least-angle regression (LARS) to determine a ranking of the performance counter inputs for use in linear and nonlinear modeling and show that the transformed performance counters are better suited for power modeling. The generated dynamic power model consisting of a nonlinear transformation block and a linear regression block reduces relative estimation error on average by 4% and in worst-case scenarios by 7% compared to state-of-the-art fine-grained linear power models. Compared to a state-of-the-art polynomial regression model our proposed approach reduces the relative estimation error by 10% in worst-case scenarios. Mark Sagi, Nguyen Anh Vu Doan, Martin Rapp, Thomas Wild, Jörg Henkel, Andreas Herkersdorf |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |