Demo Data from EDBT 2026 / reviewers in the wild / expert
Suhyeong Choi
dblp:192/7710
· DBLP profile ↗
2ranked-venue papers
2as first author
1since 2021 · last 2024
0000-0002-4665-5788ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 94% Integrated circuit design · 6% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design technology co-optimization |
0.8 | 1 | 2024 | PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation
physical design |
0.8 | 1 | 2024 | PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation › physical design
placement |
0.8 | 1 | 2024 | PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation › physical design › routing
routability |
0.8 | 1 | 2024 | PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation
design for manufacturability |
0.4 | 1 | 2019 | Neural Network Classifier-Based OPC With Imbalanced Training Data · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Electronic design automation › physical design
optical proximity correction |
0.4 | 1 | 2019 | Neural Network Classifier-Based OPC With Imbalanced Training Data · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Integrated circuit design › VLSI design
standard cell library |
0.2 | 1 | 2024 | PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation › physical design
lithography |
0.1 | 1 | 2019 | Neural Network Classifier-Based OPC With Imbalanced Training Data · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Methods — techniques the papers use, named apart from their topics
machine learning-based parameter tuning · 0.8clustering-based placement · 0.8weighted principal component analysis · 0.4synthetic data generation · 0.4polar fourier transform · 0.4neural network classifier · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design EnablementabstractWe propose a systematic framework to conduct design-technology pathfinding for power, performance, area, and cost (PPAC) in advanced nodes. Our goal is to provide a configurable, scalable generation of process design kit (PDK) and standard-cell library, spanning key scaling boosters (backside PDN and buried power rail), to explore PPAC across given technology and design parameters. We build on Cheng et al. (2022), which addressed only area and cost (AC), to include power and performance (PP) evaluations through automated generation of full design enablements. We also improve the use of artificial designs in the PPAC assessment of technology and design configurations. We generate more realistic artificial designs by applying a machine learning-based parameter tuning flow to Kim et al. (2022). We further employ clustering-based cell width-regularized placements at the core of routability assessment, enabling more realistic placement utilization and improved experimental efficiency. We evaluate PPAC across scaling boosters and artificial designs in a predictive technology node. Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2019 | Neural Network Classifier-Based OPC With Imbalanced Training DataabstractMachine learning-guided optical proximity correction, called ML-OPC in this paper, has recently been proposed to alleviate long runtime of model-based OPC. ML-OPC using regression methods has been presented but with limited prediction accuracy. We propose neural network classifier-based OPC (NNC-OPC), in which a neural network classifier serves as a mask bias model. A few techniques are applied to enhance basic NNC-OPC: parameterization of layout segments using polar Fourier transform signals, dimensionality reduction through weighted principal component analysis, and sampling of training layout segments. Training segments are typically imbalanced over the range of mask biases, which may cause large prediction error for segments that appear less frequently. This is resolved by three techniques: 1) synthetic data generation; 2) class reorganization; and 3) an adaptive learning rate. Experiments with NNC-OPC with all techniques applied indicate that prediction error of mask bias and training time are reduced by 29% and 80%, respectively, compared to state-of-the-art ML-OPC with regression methods. Suhyeong Choi, Seongbo Shim, Youngsoo Shin |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |