In this work, we present a differentiable neural architecture search (NAS) method that takes into account two competing objectives, quality of result (QoR) and quality of service (QoS) with hardware design constraints. NAS research has recently received a lot of attention due to its ability to automatically find architecture candidates that can outperform handcrafted ones. However, the NAS approach which complies with actual HW design constraints has been under-explored. A naive NAS approach for this would be to optimize a combination of two criteria of QoR and QoS, but the simple extension of the prior art often yields degenerated architectures, and suffers from a sensitive hyperparameter tuning. In this work, we propose a multi-objective differential neural architecture search, called MDARTS. MDARTS has an affordable search time and can find Pareto frontier of QoR versus QoS. We also identify the problematic gap between all the existing differentiable NAS results and those final post-processed architectures, where soft connections are binarized. This gap leads to performance degradation when the model is deployed. To mitigate this gap, we propose a separation loss that discourages indefinite connections of components by implicitly minimizing entropy.

Recent routability research has exploited a machine learning (ML)-based modeling methodologies to consider various routability factors that are derived from placement solution. These factors are very related to the circuit characteristics (e.g., pin density, routing congestion, demand of routing resources, etc), and lack of circuit benchmarks in training can lead to poor predictability for ‘unseen’ circuit designs. In this paper, we propose a machine learning (ML) framework for early routability prediction modeling. The method includes a new artificial netlist generator (ANG) that generates an artificial gate-level netlist from the user-specified topology characteristics of synthetic circuit, even with real world circuit-like. In this framework, we exploit that ANG that supports obtaining ground truths for use in training ML-based model, the training dataset that have a wide range of topological characteristics provides strong ability to inference noisy, previous-unseen data. Compared to a design-specific training dataset [4] that is used for routability prediction modeling, we increase the test accuracy of binary classification (‘pass' or ‘fail’) on timing, DRC and routability by 6.3%, 8.6% and 6.6%, and reduce the generalization error [12] by as much as 87% compared to design-specific training dataset [4].

Under process, voltage, and temperature variations, SRAM cell stability largely fluctuates from the nominal value. In the design step, SRAM cell optimization while ignoring the fluctuation induces the yield loss for the stability. Variation-aware optimization of an SRAM cell can prevent the yield loss problem by considering the mean and variance of SRAM cell stability when finding optimal design parameters. This paper proposes a novel SRAM optimization method that uses a deep neural network (DNN). Multiple DNNs from ensemble techniques represent the mean and variance of SRAM cell stability for the nominal design parameters. Subsequent sensitivity analysis of DNN extracts the K design parameters that have the most dominant effects on the mean and variance of SRAM cell stability. Then multidimensional optimization is used to find the optimal values of these K parameters to maximize the mean stability while minimizing its variance. The proposed method achieved an average of 2% error compared to MC simulation. The proposed optimization method takes only 561 s to provide the most optimal design parameter values of an SRAM cell.

Variation-aware leakage analysis becomes an essential design process as the technology node continuously shrinks. This article proposes a novel additive statistical leakage analysis method that uses exponential mixture model (EMM) to estimate the leakage distribution. Using a few leakage data for sub-blocks of an input circuit, we estimate any shape of leakage distribution regardless of new process nodes or operating conditions. Leakage distribution of an input circuit can be obtained by adding the leakage distributions of the sub-blocks. The proposed addition step sequentially adds the leakage distributions of sub-blocks that are expressed as EMMs. Before the addition step, we improve the accuracy by handling linear dependence among leakage simulation data of sub-blocks. In addition, we propose a method to reduce the number of components of an EMM to prevent exponential increase in runtime and memory during the addition process. The proposed method achieved 43.6 times improvement in goodness-of-fit of the estimated cumulative density functions compared to the best results of other analytic model-based methods.

This paper proposes a statistical approach to modeling the single-sided read static noise margin (RSNM) of a 6-transistor SRAM cell. The proposed modeling considers threshold voltage (Vth), channel length, and width variations. In addition, it considers Vth roll-off and drain-induced barrier-lowering effect of short channel transistors. The proposed method needs only a few samples to calculate the coefficients of the proposed equation. Using the calculated analytic equation, the proposed method can offer feedbacks for design improvements. In goodness-of-fit tests, the proposed method achieved about 89% and 99% improvements in the K-S statistic and the chi-square statistic compared with the Quasi-Monte Carlo method for the same number of samples. Also, compared with the previous method based on an analytic model, the proposed method achieved about 91% and 98% improvements in the goodness-of-fit tests.