This work reviews the fundamentals of the Mueller–Muller Phase Detector (MMPD) and explores its application in multilevel signaling. We analyze and highlight the advantages of adopting inner data levels for error sampling. To mitigate the worsened ISI-induced jitter in multilevel signaling, this work further proposes an unbalanced MMPD operation that improves the phase detection confidence, easing the trade-off between dithering jitter and tracking ability. Our results demonstrate that the unbalanced MMPD design effectively enhances PD gain, making it a promising solution for high-speed wireline transceivers. The unbalanced MMPD is integrated into the CDR circuit of an 80-Gb/s PAM6 receiver for verification. The receiver features a 3-bit SAR ADC with uneven slicing levels. Utilizing LSB conversion for error sampling, this ADC achieves data and error sampling without additional error samplers. Measurement results from a 28-nm CMOS prototype demonstrate higher tracking bandwidth with an eye-opening margin of over 176 mUI. At 80 Gb/s, the receiver consumes 166.5 mW with an energy efficiency of 2.08 pJ/bit.

Vector similarity search (VSS) for unstructured vectors generated via machine learning methods is a promising solution for many applications, such as face search. With increasing awareness and concern about data security requirements, there is a compelling need to store data and process VSS applications locally on edge devices rather than send data to servers for computation. However, the explosive amount of data movement from NAND storage to DRAM across memory hierarchy and data processing of the entire dataset consume enormous energy and require long latency for VSS applications. Specifically, edge devices with insufficient DRAM capacity will trigger data swap and deteriorate the execution performance. To overcome this crucial hurdle, we propose an intelligent cognition engine (ICE) with cognitive 3D NAND, featuring non-volatile in-memory computing (nvIMC) to accelerate the processing, suppress the data movement, and reduce data swap between the processor and storage. This cognitive 3D NAND features digital nvIMC techniques (i. e., ADClDAC-free approach), high-density 3D NAND, and compatibility with standard 3D NAND products with minor modifications. To facilitate parallel INT8/INT4 vector-vector multiplication (VVM) and mitigate the reliability issue of 3D NAND, we develop a bit-error-tolerance data encoding and a two’s complement-based digital accumulator. VVM can support similarity computations (e.g., cosine similarity and Euclidean distance), which are required to search “the most similar data” right where they are stored. In addition, the proposed solution can be realized on edge storage products, e.g., embedded Multi-Media Card (eMMC). The measured and simulated results on real 3D NAND chips show that ICE enhances the system execution time by $17\times to 95\times$ and energy efficiency by $11\times to 140\times$, compared to traditional von Neumann approaches using state-of-the-art edge systems with MobileFaceNet on CASIA-WebFace dataset. To the best of our knowledge, this work demonstrates the first 3D NAND-based digital nvIMC technique with measured silicon data.