This paper introduces an on-chip current-driven CMOS parametric frequency divider (PFD) that provides 2:1 frequency division with an output frequency of 2.4 GHz. A custom input driver stage with a buffer enables to generate the input current of the PFD core from a digital clock signal or sinusoidal source, and a band-pass filter (BPF) stage suppresses undesirable harmonics at the output. Analyses and discussions of design considerations provide insights into the PFD’s input driving conditions, filtering characteristics of the output driver, as well as the effects of the limited quality (Q) factor of passive components and layout parasitics. A prototype chip was fabricated in standard 65-nm CMOS technology and tested. The minimum required supply voltage for the PFD driver is 1.4 V with an input frequency of 4.8 GHz, whereas the PFD has an operating frequency range from 4.5 GHz to 5.1 GHz with a supply voltage of 1.5 V. To the best of the authors’ knowledge, the proposed PFD is the first on-chip implementation of a current-driven parametric frequency divider in a standard CMOS process with sub-6 GHz operation, which demonstrates the feasibility of on-chip integration into RF systems.

This paper presents a CMOS 2:1 differential parametric frequency divider (PFD) design with an output frequency of 2.4 GHz and an input voltage range of 450~890 mV at 4.8 GHz. The topology is suitable for integration into RF Systems-on-a-Chip (SoCs), and has been constructed for sub-6 GHz applications. A design and optimization methodology for this on-chip PFD is also described in this paper. The simulation results show a performance improvement of the proposed differential PFD compared to a single-ended PFD designed for the same output frequency in the same 65nm CMOS technology.

This article introduces an on-chip anomaly monitoring system design approach that is based on thermal profiling and side-channel analysis. The strategy aims at the realization of nonintrusive hardware Trojan (HT) detection over the lifetime of the circuit under test (CUT). To evaluate the capability of the proposed HT detection system, the on-chip electrothermal coupling is modeled as part of the simulation technique, which associates local thermal activities with circuit-level power consumption using a standard electrical simulator. To monitor the thermal profiles on chips with high sensitivity to local temperature changes and the resilience to flicker noise, the sensor architecture described in this article is the first differential temperature sensor equipped with a chopping mechanism. A methodology is described to utilize principal component analysis (PCA) to extract critical information from the quantized output of the system for effective HT detection in the presence of noise. The complete sensor signal path of the system was designed and simulated with foundry-supplied device models (130-nm CMOS technology), and the impact due to process variations have been considered via Monte Carlo simulations. The results indicate that small Trojans with approximately 2 μW of power can be detected within the thermal profile of a CUT consuming more than 500 μW. As the first step to prove the feasibility of on-chip quantization in the HT detection system, a prototype 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) was fabricated with 130-nm CMOS technology.