This paper presents a dual-band architecture, which combines radio-frequency energy harvesting (RFEH) and a wake-up receiver (WuRX) for wireless sensor networks (WSNs). By separating the wake-up and energy-harvesting frequency bands, the design eliminates co-channel interference (CCI), improving wake-up sensitivity. To achieve high integration, a frequency-blocking single-balun time-division multiplexing (FB-TDM) is proposed, enabling RFEH and WuRX to share antenna (ANT), matching network (MN), and balun across different frequency bands, without high-loss MOS switches or bulky off-chip filters. Moreover, to address missed detection caused by time division multiplexing (TDM), discontinuity-tolerant coding and correlator are proposed. The self-powered WuRX is implemented in a 65nm CMOS process, occupying an active area of 0.33 mm2. The measurement results show that the chip can harvest RF energy at -35 dBm with a DC output exceeding 0.45 V, and supports wake-up reception at -55 dBm with 50 bps data rate, 158 ms latency, and an energy cost of 3.712 nJ per activation.

This paper presents a PVT-insensitive and wide electrode DC offset (EDO) elimination range bio-signal instrumentation amplifier (Bio-IA). A bulk-driven bias voltage adaptive adjustment (BD-VAA) OTA is proposed to effectively suppress the leakage current of the input transistors’ gate in the amplifier, thus stabilizing the bias voltage of the Bio-IA. In addition, a pre-feedback analog DC servo loop (PF-ADSL) based on an expanded input-stage (EIS) fully differential difference amplifier (DDA) buffer is proposed to increase the EDO elimination range. Each input stage in the DDA employs the improved parasitic capacitance shielding (IPCS) technique, which significantly enhances both the common-mode (CM) input impedance and the differential-mode (DM) input impedance. The Bio-IA is implemented based on a 65 nm CMOS process. Measurement results indicate that the input bias voltage of the Bio-IA is stable. The EDO elimination range of the Bio-IA is extended to$\pm ~240$mV, the CM input impedance of the Bio-IA is as high as 39.9G$\Omega $, and the DM input impedance reaches 5.2 G$\Omega $.

This paper presents a high-efficiency, wide-input power range ambient Radio Frequency Energy Harvester (RFEH) system, which comprises an adaptive 4-mode impedance matching network (IMN), a single-stage cross-coupled differential-drive (CCDD) rectifier, a maximum power point tracking (MPPT) circuit, and a power manager unit (PMU). To adaptively configure the impedance matching network and modulate the TONof the buck-boost converter, a feedback-free fast (F3) MPPT technique based on the input power detection and parameters direct adjustment is proposed. It can effectively address the trade-off between the speed and accuracy in the impedance matching as well as in the maximum power transmission. Therefore, the power conversion efficiency (PCE) of the proposed RFEH system has been greatly improved. The power manager unit (PMU) is composed of a buck-boost converter, a self-supply unit, and a load regulator, which is employed to implement the F3MPPT, startup, and self-powered of the RFEH system. The proposed design is fabricated in a 0.18-$\mu $m CMOS technology, and the chip area is about$1.52\times 0.78$mm2. The measurement results demonstrate that the proposed RFEH system can operate in a wide PINrange of −23 to 1 dBm with over 96% MPPT accuracy. It achieves PCE >20% in the PINrange of −17 dBm to 1 dBm, with a peak PCE of 49.4% at P$_{\mathrm {IN}}= -5$dBm.

This article proposes a dual-input-dual-output (DIDO) dc-dc hybrid interface for thermoelectric energy harvesting (TEH) applications with high efficiency and low output ripple. A load-first ordered power distributive control (OPDC) strategy is used to recycle the excess thermoelectric energy (TE) in time. Utilizing the digital adaptiveon-time (DAOT) technique, the output ripple can be reduced during battery (BAT) power supply. A hysteresis-controlled maximum power point tracking (MPPT) technique is proposed to track the variation of the internal resistance$\text {R}_{\text {TE}}$of the thermoelectric generator (TEG), which achieves high tracking efficiency over a wide$\text {R}_{\text {TE}}$range. By trading the tracking efficiency and loss off in the MPPT, an optimization method for hysteresis window is proposed. In addition, an analog zero-crossing detector (ZCD) without calibration is adopted to improve the end-to-end efficiency. The proposed hybrid interface is realized by 0.18-$\mu $m standard CMOS process with a core area of$0.91 \times 0.61$mm2. Measured results show that the proposed interface can harvest TE over the$\text {R}_{\text {TE}}$variation range of 1–$1000 \; \Omega $, with a peak tracking efficiency of 99.6% and an output ripple as low as 35 mV. It also achieves a peak end-to-end efficiency of 87% and an output power range of$1 \; \mu $W −10 mW.

This paper demonstrates a low-noise, offset and temperature coefficient (TC) bandgap reference for the portable biopotential signal monitoring system. The proposed feedback coefficient enhancement technique suppresses the low-frequency noise and offset voltage. Besides, the bowl-shaped curvature compensation is applied in the BGR to obtain a decent TC. The proposed bandgap reference was designed and fabricated by the$0.18 ~\mu \text{m}$deep N-well CMOS technology with an active area of 0.088 mm2. Experimental results show that this BGR outputs 0.6 V reference voltage under 1.2 V supply voltage while consuming$60 ~\mu \text{W}$power. The measured integrated noise from 0.1 to 10 Hz is about$3.0 ~\mu \text{V}$(rms). In addition, the average TC of the BGR is 2.4 ppm /°C from −45 °C to 125 °C after trimming.

In order to improve the efficiency over a wide load range, a power converter of the Internet of Things (IoT) usually works in dual modes, which are pulsewidth modulation (PWM) and pulse frequency modulation (PFM). A mixed load detection scheme is adopted to enable the appropriate modes under different loads, whose analog detector has an accurate detection in the heavy load, and the digital load detection improves the light-load efficiency. When the power converter operates in different modes, the control loops are different. Meanwhile, a seamless mode transition technique (SMTT) is presented in this article to improve the transient response during mode change between PWM and PFM. A test chip was fabricated in a 0.18-$\mu $m standard CMOS process, and the chip area is$1.59\times 1.37$mm2. The experimental results show that the efficiency is above 85.3% under$V_{\text {IN}}=3.3$V,$V_{\text {OUT}}=1.8$V, and in the load range from 1 to 300 mA, while peak efficiency can reach 96.1% at 100-mA load. Compared to the case without the proposed technique, the under/overshoot voltage can be reduced by above 55% during the mode transition.

This paper proposed a hybrid energy harvesting interface for wearable electronic devices, which achieves the simultaneous harvesting of piezoelectric and thermoelectric energy from the human body. The interface employs an inductor-shared converter with maximum power point tracking (MPPT) assistance to convert the piezoelectric energy rectified by a parallel synchronized switch harvesting on capacitor (P-SSHC) rectifier and the thermoelectric energy into a regulated output. The harvester employs an adaptive switching cycle (ASC) scheme to reduce the ripple of the tracking to improve the MPPT accuracy and end-to-end efficiency. In parallel, for efficient harvesting of both sources simultaneously, a multiplexed MPPT technique is incorporated into the harvester to reduce the chip area. In addition, to reduce the power loss resulting from the sampling phase of the FOCV method, a single-cycle fast-sampling technique is employed to assist the piezoelectric energy harvesting. The proposed hybrid energy harvester is fabricated by a$0.18 \mu \text{m}$CMOS process with a core area of$1.2 \times 0.7$mm2. The measured results show that the peak tracking efficiency of the PZT and TEG is 99.58% and 99.37%, respectively. The peak of end-to-end efficiency of the interface reaches 86.67%.

This paper proposes a low-noise and low-power current-reuse analog front-end (AFE) for multi-channel electrocardiography (ECG) acquisition. A new low-power orthogonal recombination method is proposed in the four-channel current-reuse amplifier, which reduces the recombination current by half and cuts down the power supply voltage while ensuring the crosstalk suppression capability, resulting in a lower average channel power consumption. A four-order current-cancellation subthreshold-source-follower low-pass filter (CS-LPF) is proposed in this paper, which realizes the reduction of the chip area and power consumption by cross-coupling current cancellation technology. In addition, the input impedance boosting circuit, DC servo loop (DSL), and successive approximation register analog-to-digital converter (SAR-ADC) are designed in the proposed AFE, and it can record and quantify ECG signals. The presented AFE was implemented in a 65nm CMOS process, and the core area is 1.42mm$\times 0.85$mm. The measured results show that the proposed AFE has a variable gain of 40.5-56dB. The fully differential low-pass filter with a power consumption of only 4.8nW achieves 50% capacitance reduction. The average power consumption per channel of the proposed AFE is only$2.6\mu \text{W}$, and the power efficiency factor (PEF) and noise efficiency factor (NEF) are 3.93 and 1.81 respectively.

This article presents a 0.4-V startup, dead-zone-free, monolithic four-mode synchronous Buck-Boost converter. By introducing constant frequency transition-Buck (T-Buck) mode and transition-Boost (T-Boost) mode in the transition region, the dead-zone problem of the dual-mode Buck-Boost converter and the inefficiency of the single-mode converter can be effectively solved. In addition, this article adopts the adaptive peak and valley current control and designs a reused slope compensation circuit, which reduces the converter’s static power consumption and improves the light load efficiency of the converter. To widen the input voltage range of the converter, a low-voltage startup scheme without off-chip auxiliary components and low-$V_{\mathrm {TH}}$MOSFETs is proposed. The startup voltage is reduced to 0.4 V at a lower cost, and it greatly broadens the input voltage range of the monolithic converter. The proposed converter has been implemented in a standard 0.18-$\mu \text{m}$CMOS process occupying a die area of 1.7 × 2.0 mm. The test results show that the converter with an input range of 0.4–3.3 V and an output voltage of 1.8 V. The peak efficiency can reach 90.8% at 100 mA and the light load efficiency can reach 85% at 10 mA. Besides, the efficiency in the transition region of 1.44–2.25 V is higher than 80%.

This paper presents a fully differential wake-up receiver (WuRX) with ultra-low power and high sensitivity. Implementing the fully differential framework achieves differential signal processing without an off-chip balun, which achieves noise suppression and sensitivity improvement. The low voltage baseband signal processing (LVBSP) is proposed to cut down the power consumption, which is achieved by the low-voltage fast-response differential amplifier (LFDA) and the time-domain signal processing circuit. Moreover, the periodic offset cancellation technique (POCT) in the baseband circuit is proposed to alleviate the offset and low-frequency noise impacts. This WuRX is implemented in the TSMC 65-nm CMOS process occupying an active area of 0.18 mm2. When operating at 434 MHz, the proposed WuRX has a −75-dBm sensitivity at 250 bps while consuming 6.4 nW from 0.4 V supply voltage.

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a$0.18 \mu \text{m}$standard CMOS process, which occupies a chip core area of about 1.0 mm$\times0.9$mm. It achieves >60% efficiency in the range of TEG open-circuit voltage$V_{S}$from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the$V_{S}$as low as 10 mV can be achieved.

This article presents a low supply voltage and low-power charge-pump phase-locked loop (CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The$V_{\mathrm {ref}}$adaptive adjustment mechanism is analyzed in the class-C voltage-controlled oscillator (VCO) with dual-mixed loops, which eliminates the PN’s sensitivity to temperature and process. Moreover, based on resistance-based accurate current replication, the low-power and low-current mismatch charge-pump (CP) circuit structure is proposed to reduce the reference spur of the PLL. In addition, by using the dynamic current compensation scheme, the power consumption of the CP is greatly reduced. The proposed PLL is fabricated in a 0.18-$\mu \text{m}$RF CMOS process with an area of 1.07$\times $1.07 mm2. The measurement results show that the proposed PLL achieves a 2.24–2.85-GHz frequency tuning range and a PN of −123.97 dBc/Hz at 1-MHz offset from a 2.55-GHz carrier. The measured reference spur is −89.4 dBc at 40-MHz offset frequency and the total power consumption is 2.62 mW at the 0.8-V power supply voltage.