In recent years, it has been observed the exponential growth of the Internet of Things (IoT) in different application fields, such as manufacturing and energy industry. To effectively fuse and process the tremendous amount of IoT sensing data timely, there is an urgent need to shift from a conventional centralized computing to a decentralized computing. However, there remain some essential technical challenges to develop effective decentralized computing methods in the context of IoT applications, including 1) the timely response, sufficient privacy preservation, and high security are normally required in IoT-related applications and 2) the biases and non-independent identically distributed (IID) properties potentially presented in the IoT sensing data. To address these challenges, in this article, we propose a decentralized deep learning paradigm with privacy-preservation and fast few-shot learning (DDLPF) by exploiting federated learning, metalearning, and blockchain techniques. In the simulation section, we evaluate the performance of our proposed DDLPF paradigm in different scenarios and compare it with other existing techniques.

A joint numerical representation based on both Gaussian and Eisenstein integers is proposed. This Gauss-Eisenstein representation maps complex numbers into four-tuples of integers with arbitrarily high precision. The representation furnishes the computation of the 3-, 6-, and 12-point discrete Fourier transform (DFT) at any desired accuracy. The associated fast algorithms based on the Gauss-Eisenstein integers are error-free up to the final reconstruction step, which can be realized in hardware as a multiplierless implementation. The introduced methods are compared with competing algorithms in terms of arithmetic complexity. We propose three FRS architectures based on the following methods: Dempster-McLeod representation, expansion factor, and addition aware quantization. The Gauss-Eisenstein 12-point DFT is physically realized on a Xilinx Virtex 6 FPGA device with maximum clock frequency of 302 MHz for the expansion factor FRS with real-time throughput of 3:62 × 109 coefficients/s. The FPGA verified digital designs were synthesized, mapped, placed and finally routed for 0:18mm CMOS technology assuming a 1.8 V DC supply employing Austria Micro Systems (AMS) standard-cell library (hitkit version 4.11). The routed ASIC is predicted to operate at a maximum frequency of 505 MHz for the expansion factor FRS with potential real-time throughput of 6:06 × 109coefficients/s.