This paper presents an energy-efficient spike-sorting system-on-chip (SoC) designed for closed-loop brain-computer interfaces of massive probing channels. The design first incorporates a sparsity/similarity-aware spike detection scratchpad, leveraging a bit-wise differential encoder and zero-friendly read-out circuits, reducing the dynamic power consumption of spike detection by 77.7%. To mitigate static power dissipation, it also introduces an ultra-low-leakage dual-voltage 5T-SRAM array with level-shifter embedded sense amplifiers, achieving an 82.2% leakage power reduction of neural signal buffering by applying half$V_{DD}$on SRAM cells. Additionally, a memory hierarchy architecture combining on-chip SRAM and off-chip FeRAM, along with a firing-rate-based Osort for cluster template management, minimizes off-chip memory access to only 9.7% with a latency of$11.7\mu $s for 1024-channel spike sorting. A silicon prototype is fabricated in 28-nm CMOS technology, which achieves a power consumption of 583nW/channel and an area consumption of 0.0012mm2/channel. The chip supports real-time spike sorting with up to 16K templates,$21.3\times $greater than the state-of-the-art spike-sorting processor.

This work presents a picowatt self-biased and self-compensated CMOS voltage reference for high-accuracy and ultra-low-power applications. By self-compensating the reverse-biased diode leakage (RBDL) in the core transistors which work in the subthreshold regions, the proposed design simultaneously achieves extremely low power consumption and wide operating-temperature range, without degrading the output accuracy. Fabricated in a 0.18-μm CMOS technology, the circuit occupies an area of 0.009 mm2. The measured results indicate that the designed circuit can generate an average voltage reference of 330 mV with a standard deviation of 2.6 mV at room temperature. With the proposed self-compensation scheme, the average temperature coefficient of 10 dies is 94 ppm/°C over a wide temperature range of 190 °C (from −40 °C to 150 °C). Moreover, it consumes only 70 pW at room temperature and achieves a line sensitivity of 0.07%/V.

Be aware of the significance of land surface net radiation ($R_{n}$), there is a need for accurate long-term and high spatial resolution global$R_{n}$estimates based on satellite data. Herein, we propose a novel globally applicable, highly effective algorithm for estimating daily$R_{n}$directly from Visible Infrared Imaging Radiometer Suite (VIIRS) top-of-atmosphere (TOA) observations ranging from 2011 to present, using the eXtreme Gradient Boosting (XGBoost) method. This algorithm, named the constraint conditional model (CCM), consists of five conditional models (namely, cases 1–5 model) divided by the combination of the length of daytime (dt), the instantaneous sky condition, and the surface broadband albedo, and the daily downward shortwave radiation (DSR) from ERA5-Land was introduced as a physical constraint when$dt \gt 9$, in which case$R_{n}$is dominated by$R_{\textit {si}}$(incoming solar radiation). The validation accuracy of CCM was satisfactory against the ground measurements, yielding a root-mean-square error (RMSE) of 18.95 Wm−2, a bias of 0.056 Wm−2, and an$R^{2}$of 0.89. The algorithm exhibited superior accuracy and robustness compared to GLASS-MODIS and ERA5-Land under spatiotemporally independent validation samples. This indicates the potential of VIIRS to extent MODIS$R_{n}$products for generating long-term global daily$R_{n}$data.

Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of$\mathbf{2.53} \mu \mathbf{W}/\mathbf{channel}$and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

Network-on-chips (NoCs) continues to be the choice of communication fabric in multicore architectures because the NoC effectively combines the resource efficiency of the bus with the parallelizability of the crossbar. As NoC suffers from both high static and dynamic energy consumption, power-gating and dynamic voltage and frequency scaling (DVFS) have been proposed in the literature to improve energy-efficiency. In this work, we propose DozzNoC, an adaptable power management technique that effectively combines power-gating and DVFS techniques to target both static power and dynamic energy reduction with a single inductor multiple output (SIMO) voltage regulator. The proposed power management design is further enhanced by machine learning techniques that predict future traffic load for proactive DVFS mode selection. DozzNoC utilizes a SIMO voltage regulator scheme that allows for fast, low-powered, and independently power-gated or voltage scaled routers such that each router and its outgoing links share the same voltage/frequency domain. Our simulation results using PARSEC and Splash-2 benchmarks on an 8 × 8 mesh network show that for a decrease of 7% in throughput, we can achieve an average dynamic energy savings of 25% and an average static power reduction of 53%.

“BitLab” is an innovative classroom that integrates scientific history, sensor technology with quick prototyping and public speaking in a team-based interactive learning environment. In order to inspire the students' spirit of innovation, everything in this classroom is built by small “Bit”. Electronic sensor-based “BitLab Bricks” enable the students to conceive their own innovative design, which covers daily life applications. A prototype is then built using geometric shapes. In the end, each team writes up a description of their “product” and gives a presentation on its features and functionalities. The interactive learning platform is delivered through team-based “BitLab Curriculum”. The status and impact of BitLab in Chinese schools are presented.