Wheeled robot fault diagnosis is indispensable for ensuring its reliable and safe operations. However, two challenges impede the application of prevalent intelligent diagnosis methods. 1) Multisensor fusion: The complexity of robot movements necessitates multisensor for comprehensive monitoring, generating strong-coupled, and high-dimensional data that complicate both intrinsic relationship mining and effective fusion; 2) Heterogeneous data silos: Dispersibility, heterogeneity and privacy constraints across different robots lead to non-independent and identically distributed (Non-IID) data silos, severely limiting the development of universal diagnostic models. To overcome these two problems, this article proposes a tailored federated physics-informed graph framework (FedMA-PIG). On the client side, the kinematics mathematical model is constructed for each robot, which explores the inter-sensor correlations and forms a physics-informed graph. It enables multisensor data fusion and assists the client in training a local graph neural network. On the federated framework side, a Non-IID federated framework based on a multianchor contrastive mechanism is devised. It employs multiple anchors to capture common knowledge from heterogeneous robot data, guiding feature representations toward corresponding anchors and away from others, thereby promoting consistency and mitigating inter-client data heterogeneity. Comprehensive experiments were conducted on three representative wheeled robots- Mecanum-wheeled, 4WD-wheeled, and Omni-wheeled- distributed across four federated clients. The results demonstrate that FedMA-PIG achieves generalized and superior diagnostic performance compared to state-of-the-art methods.

The increased demand for data privacy and security in machine learning (ML) applications has put impetus on effective edge training on Internet-of-Things (IoT) nodes. Edge training aims to leverage speed, energy efficiency and adaptability within the resource constraints of the nodes. Deploying and training Deep Neural Networks (DNNs)-based models at the edge, although accurate, posit significant challenges from the back-propagation algorithm’s complexity, bit precision trade-offs, and heterogeneity of DNN layers. This paper presents a Dynamic Tsetlin Machine (DTM) training accelerator as an alternative to DNN implementations. DTM utilizes logic-based on-chip inference with finite-state automata-driven learning within the same Field Programmable Gate Array (FPGA) package. Underpinned on the Vanilla and Coalesced Tsetlin Machine algorithms, the dynamic aspect of the accelerator design allows for a run-time reconfiguration targeting different datasets, model architectures, and model sizes without resynthesis. This makes the DTM suitable for targeting multivariate sensor-based edge tasks. Compared to DNNs, DTM trains with fewer multiply-accumulates, devoid of derivative computation. It is a data-centric ML algorithm that learns by aligning Tsetlin automata with input data to form logical propositions enabling efficient Look-up-Table (LUT) mapping and frugal Block RAM usage in FPGA training implementations. The proposed accelerator offers 2.54x more Giga operations per second per Watt (GOP/s per W) and uses 6x less power than the next-best comparable design.

System-on-Chip Field-Programmable Gate Arrays (SoC-FPGAs) offer significant throughput gains for machine learning (ML) edge inference applications via the design of co-processor accelerator systems. However, the design effort for training and translating ML models into SoC-FPGA solutions can be substantial and requires specialist knowledge aware trade-offs between model performance, power consumption, latency and resource utilization. Contrary to other ML algorithms, Tsetlin Machine (TM) performs classification by forming logic proposition between boolean actions from the Tsetlin Automata (the learning elements) and boolean input features. A trained TM model, usually, exhibits high sparsity and considerable overlapping of these logic propositions both within and among the classes. The model, thus, can be translated to RTL-level design using a miniscule number of AND and NOT gates. This paper presents MATADOR, an automated boolean-to-silicon tool with GUI interface capable of implementing optimized accelerator design of the TM model onto SoC-FPGA for inference at the edge. It offers automation of the full development pipeline: model training, system level design generation, design verification and deployment. It makes use of the logic sharing that ensues from propositional overlap and creates a compact design by effectively utilizing the TM model's sparsity. MATADOR accelerator designs are shown to be up to 13.4x faster, up to 7x more resource frugal and up to 2x more power efficient when compared to the state-of-the-art Quantized and Binary Deep Neural Network implementations.

Industrial blockchain is believed to be a promising technology for modern industries. Despite the capacity of blockchain to protect users’ privacy, its inherent transparency renders data provenance traceable, a situation that does not fully guarantee the confidentiality of users and data sources. Users’ preferences, habits, identity, and other sensitive privacy information can be analyzed by adversaries after collecting a series of users’ requests. This paper integrates existing oracle technologies and proposes a distributed oracle architecture DISOC based on TOTP and ring signature to overcome the privacy shortcomings of traditional oracles. DISOC can be used to implement trustworthy off-chain data sharing from different data source with strong privacy-preservation. It can effectively protect the privacy of data sources while protecting user privacy to mitigate potential data leakage issues. After analysis and testing, DISOC can perfectly meet the data sharing needs and privacy preservation of multiple data sources.

Tsetlin machines (TMs) are a novel machine learning paradigm based on learning automata and Boolean logic inference, with better energy-efficiency and explainability than neural networks. This work exploits non-volatile ReRAM-transistor memory arrays to perform efficient in-memory TM computing. To accommodate the large timing variability of ReRAM devices and enhance energy efficiency and speed, the control path is implemented with quasi delay-insensitive (QDI) asynchronous circuits. The design of these circuits are derived and synthesized from their signal-transition graph specifications using the Workcraft tool. The resulting circuits offer high event-driven controllability and high variation tolerance for the mixed-signal ReRAM data path. Compared to state of the art TM hardware, the new TM design uses less than 5% of the power to achieve better than$4\times$the performance.

As a nonlinear measure, Lempel–Ziv complexity (LZC) can be considered as a suitable parameter for characterizing bearing health status by measuring the complexity of vibration signals. However, in continuous monitoring scenario under noisy condition, all components of a multicomponent bearing signal are not equally sensitive toward a change of LZC value. As a result, a direct application of LZC for bearing health monitoring not only suffers from its inefficient early fault warning but also fails to infer the fault progression. In this article, instead of direct utilization of a whole vibration signal, its fundamental component (FC) sensitive to LZC calculation is separated with the help of continuously adjustable parameterized tunable$Q$factor wavelet transform (TQWT). In this context, a study based on sparsity indices has been done for$Q$factor selection of TQWT. Since TQWT uses an oscillation-based bearing FC separation scheme for LZC calculation, the proposed measure is termed as oscillatory Lempel–Ziv complexity (OLZC). Two experimental cases are used for validation. Performance of OLZC is compared with original LZC, representative sparsity indices and recently proposed multiscale symbolic Lempel–Ziv complexity. Results demonstrate that the proposed OLZC can not only overcome the limitations of the original LZC but also performs better than other indices in comparison to continuous monitoring of bearing health.

This paper presents a novel design method for asynchronous control logic targeting successive approximation register (SAR) analog-to-digital converters (ADCs). This work is based on modeling the control logic for SAR ADCs using signal transition graphs (STGs). Different from conventional synchronous controllers, the proposed method results in asynchronous controllers driven by the causality of signals rather than relying on clocks to control the conversion process. Moreover, the proposed asynchronous control logic can be modularized through the handshake protocol, making it possible to build ADCs of arbitrary precision based on single-bit control units. This work results in a formal, model-based asynchronous design flow for SAR ADC control, which is shown to produce resulting circuits of similar speeds but great power efficiency improvements.