Automotive Ethernet is considered to be the backbone of future in-vehicle data communication. One main feature is its ability to simultaneously transmit data and energy via power over data lines (PoDL). This article proposes the design of a single-ended high-voltage (HV)-compliant 11-bit current-steering digital-to-analog converter (DAC). The converter is tailored for the utilization as digitally controlled current source in an adaptive noise-cancellation filter for PoDL networks. Designed in an HV-compliant 180-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) semiconductor technology, the DAC features a monolithically combined topology of two identical 10-bit low-voltage (LV) current-steering DACs supplied at 1.8 V and two complementary HV-compliant output current stages. Main design features of the segmented LV DAC are the utilization of single-ended current cells with an optimized switching logic, proposed to enhance the cells transient performance and energy efficiency. Furthermore, a newly derived$Q^{4}$asymmetric rotated walk switching scheme is investigated. At a maximum output voltage of 60 V, the proposed DAC can deliver a bidirectional output current with the amplitudes of up to 500 mA. The proposed DAC exhibits the highest voltage compliance combined with the highest output current compared with related works. It also features the second highest resolution. Operated at a sample rate of 10 MS/s with a resolution of 11 bit, a spurious-free dynamic range (SFDR) of 57.8 dB could be measured for a synthesized single tone at 100 kHz, as well as a maximum integral nonlinearity (INL) error of 1.61 LSB and a differential nonlinearity (DNL) error of 1.05 LSB.

A dynamic element matching (DEM) decoder with integrated mismatch calibration control for high-speed current-steering digital-to-analog converters (CS-DACs) and CSDAC- based direct digital frequency synthesizers (DDFSs) is studied and presented. The DEM algorithm achieves very good averaging of mismatch-induced errors in the succeeding CS-DAC. It features a minimum element transition rate, therefore opimizing the power dissipation and ensuring minimal glitch energy at the output. Due to the chosen network-based architecture, with only a few modifications of the hardware, the decoder allows the integration of a comprehensive current source mismatch calibration that can be fully operated in the background and even in parallel to the regular DEM operation. A proof-ofconcept hardware implementation of the presented decoder was fabricated in a 22-nm FD-SOI CMOS process and characterized in a high-speed DDFS system with a sampling rate of 5 GHz. Measurements reveal a significant improvement in the spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) when the calibration and DEM are enabled. Compared to the state-of-the-art (SoA), the presented DDFS achieves one of the best figures of merit.

In this research paper, a concept for a 225 GHz frequency quadrupler with phase control in local oscillator paths is investigated. By combining a 56.25 GHz phase shifter with a millimeter wave quadrupler, producing a 225GHz signal, a highly performant way of realizing phase control at up to sub-THz frequencies is studied. Locating the phase shifter in the sub 60GHz band both enhances the phase control and overall gain of the system. A phase control range of 330° is measured. With a de power consumption of 105mW, the system achieves a maximum output power of 0.16dBm and a maximum gain of 21dB outperforming the state of the art by 17dB and 25dB respectively. This results in a factor 40 and 2.5 improvement of drain and gain efficiency respectively. Additionally, the root mean square (rms) gain error is reduced to best in class value of 0.04 dB while maintaining a competitive rms phase error of 4.7°.

This paper presents the design and characterization of a low power 20 Gb/s 1:4 demultiplexer (Demux) in 45-nm SOI CMOS. For the design of the latch, which is used primarily inside the key building blocks of the 1:4 Demux, a power-speed optimized current-scaling methodology is provided. The results of an electromagnetic (EM) 3D field solver, which was used to simulate the high-frequency performance of the most critical data and clock paths inside the Demux, are presented. The designed 1:4 Demux uses a supply voltage of 1 V, dissipates a total of 77 mW of power, and occupies an active area of 0.122mm2. Among the reported inductorless CMOS 20 Gb/s 1:4 Demuxes, the presented Demux achieves the best energy figure of 3.8 pJ/bit.

In differential signaling systems using copper wires common mode signals are the cause of emission of electromagnetic energy. Especially in Automotive Ethernet systems this is a challenging problem. Beside classical passive components like common mode chokes active circuits can help to reduce the emission. This allows inexpensive and resource-conserving unshielded twisted pair cables to be used. This paper shows the approach of using a mixed-signal control loop based on a comparator and a 8 bit DAC for regulating the common mode voltage of an Automotive Ethernet DAC in 28 nm CMOS. An attenuation for interferers with frequencies up to 500 kHz is achieved and reaches up to 15 dB at maximum. The control loop utilizes the successive approximation algorithm commonly used for delay locked loops and DC trimming in mixed-signal circuits. In contrast to known applications the performance and usability at higher frequencies is considered in this paper. Being a nonlinear, time-variant system an analytical design of the control loop is very difficult. Therefore parametrical measurements show the dependency of frequency, amplitude and signal form of an applied common mode interferer source.