This work presents a high-efficiency, high-density, and high-speed on-substrate-integrated buck converter for power delivery in mobile devices. This converter employs an advanced on-substrate packaging technique, which integrates all the power devices and capacitors within a compact$5\times 6\times 0.3$mm footprint, making it particularly suitable for space-constrained mobile applications that require fine-grained power management for digital cores. The proposed converter features a two-stage, two-phase architecture and cooperative dynamic frequency control, achieving a 19.1% efficiency improvement under light-load conditions. Fabricated in a 65-nm CMOS process, the converter operates at an 8-MHz per-phase switching frequency and delivers an output voltage range of 0.5–1 V. This design achieves a peak efficiency of 91% and maintains efficiency above 80% over a load range of 0.2–7 A. The power density reaches 0.93 W/mm2.

This article presents a two-stage pipelined noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution applications. However, it asks for an accurate residue amplification to avoid severe quantization noise leakage from the frontend stage. Therefore, a charge-efficient correlated-level-shifting (CECLS) assisted residue amplifier (RA) is designed by inserting the level-shifting network (LSN) in a two-stage floating inverter amplifier (FIA). In addition to the inherited low-power merit from FIA, it boosts the equivalent open-loop gain to 92 dB while preventing bandwidth reduction and charge-sharing effects, making the amplification more accurate and faster than prior CLS-assisted amplifiers. The prototype is fabricated using 55 nm CMOS technology and occupies an active area of 0.26 mm$^{\mathbf {2}}$. The measurement results show a 96.2 dB peak-SNDR and 871 nW power consumption under a 1.2 V supply voltage with a 16 kS/s sampling rate. Compared to the recent state-of-the-art ADCs with power under$10\mu $W and SNDR exceeding 90 dB, this ADC presents the best Schreier FoM of 180.8 dB.

This paper presents a 96.5% peak efficiency adaptive ON-time controlled buck converter with 0.001-500 mA load range for internet of things. A novel positive feedback controlled comparator is presented, with its bias current dynamically increased to accelerate the transient responses while maintaining low power consumption. Besides, the power gating scheme and a sub-nA voltage reference is implemented to achieve ultra-low overall quiescent current, leading to an outstanding conversion efficiency. Designed and simulated in a 0.18μm CMOS process, the prototype shows an undershoot voltage of 43 mV and recovery time of 2.8 µs during a load transient from 10 μA to 500 mA, with a total quiescent current of 60 nA. The proposed design shows efficiencies of 95.4%, 96.5% and 91.2% when the load current is 10 μA, 100 μA, and 500 mA, respectively.

This article presents a novel Dickson hybrid boost converter for thermoelectric energy harvesting that utilizes a fixed ratio switched-capacitor (SC) converter combined with a traditional switched-inductor design. This unique approach makes high conversion ratio (CR) more attainable. Besides, the converter features an on-chip LC oscillator for cold-starting the harvester without requiring any external components. To improve the efficiency of the harvester, a lookup table-based maximum power point tracking (MPPT) and a zero current detection (ZCD) circuit are also implemented. The prototype was designed and fabricated using the 55 nm low power (LP) CMOS process, with a compact 5.6-$\mu $H inductor. Measurement results verify that the harvester can cold start at an open-circuit voltage ofV$_{\mathbf{TG}}$$=$110mV, achieve a peak efficiency of 90.5% atV$_{\mathbf{TG}}$$=$140mV, and maintain operation at a 5-mV input voltage with a 200-nA load. Furthermore, the converter maintains end-to-end efficiencies above 80% for a wide range ofV$_{\mathbf{TG}}$$=$40$\sim$200mV. With a wide input range of 5$\sim$100mV and load range of 200nA$\sim$4.52mA, the proposed converter represents a significant improvement in performance over previous state-of-the-art designs, with a decent power efficiency, compact form factor and wide output power range.

This article presents a wide voltage and current range bypass-assist series-capacitor power converter for data centers and automotive applications. The overall power converter consists of a 2:1 charge pump (CP) front stage and a 6-level bypass-assist series-capacitor rear stage, by which the proposed design resolves the troublesome duty cycle limit that a typical series-capacitor converter usually faces. Therefore, the output regulation range is significantly extended and only one inductor is required. Besides, since the converter operates like a simple Buck converter with an equivalent input of$V_{\mathrm {IN}}$/12, an easy pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) compatible design is implemented and the efficiency greatly enhanced over a wide load range. The prototype was fabricated using the 180 nm bipolar-CMOS-DMOS (BCD) process and demonstrates a broad operating voltage range of 36~55-V input and 0.6~2.5-V output with 1.5mA~5A load range. For a typical 48-V input, the measured peak efficiencies of 2.5, 1.8, 1 and 0.6-V output are 93.1%, 88.1%, 86.6% and 82.7%, respectively. Additionally, when the load decreases to 30-mA, the proposed converter still achieves efficiencies of 88%, 82%, 80% and 70%, respectively.

This paper presents a Dickson hybrid boost converter with an on-chip cold starter for thermoelectric energy harvesting. The proposed harvester achieves both high power efficiency and low inductor volume. An on-chip LC oscillator cold starts the harvester without external components. Besides, a lookup table based maximum power point tracking (MPPT) improves the end-to-end efficiency in a wide input range. Designed and simulated in a 0.13 $\mu$m CMOS process, the harvester achieves a maximum end-to-end efficiency of 93.9% with a 5.6 $\mu$H inductor. The circuit cold starts at an input of 70 mV and the minimum operation voltage is as low as 6 mV with a 100 nW load.