Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions.

With functional safety being increasingly important in the development of mixed-signal products for automotive applications, EDA solutions have appeared striving to help designers in the setup and execution of fault injection campaigns. Despite the ongoing work to standardize the definition of defect models and coverage calculation methods in the IEEE P2427 draft standard, there is a lack of a unified and portable method to define defect templates that can be used to inject in a systematic way defects in an analog circuit. Each of the existing EDA tool sets for fault injection proposes its own proprietary method to specify how defects should be defined and injected. The proposed paper describes a Verilog-A-based approach to coding defect templates, which through compliance with the Verilog-A standard, warrants portability across compatible simulators. The approach has been validated on the circuits from the Analogue Benchmark Circuits made available by the IEEE P2427 working group.

In this article, a predictive fault grouping based on the collection of faulty AC matrices at fault-free operating points is presented as a means to approximate the final distribution of faults in equivalence classes using a minimal computational effort. The method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself only to AC simulations with faults activated. The technique provides an approximation, since it does not characterize faults at the corresponding faulty operating point but instead looks at how they would modify the fault-free operating point once injected.The approximate grouping achieves an excellent correlation to the final classification based on the comparison of faulty transient wave-forms. It is not meant as a substitute for the traditional fault injection simulations but as a support to decision making. It allows prioritizing faults to characterize the possible failure modes with a minimum number of fault injections, pushing out fault injections which are estimated to marginally increase the learning.

There are plentiful successors of SPICE language for describing transistor-level designs. For most of them, the semantic matches those of SPICE, and only the syntax is changed. Others instead provide more default models or analysis tools. Consequently, a commercial tool is usually required for simulating, analyzing, and especially manipulating these languages. This article proposes a framework that relies on the shared semantic for reading, writing, or manipulating transistor-level designs. The ultimate goal of the framework is: reading an input design written in a specific syntax and then allowing to write the same design in another syntax. First, the input description is parsed by a language-specific front-end which turns it into an in-memory abstract syntax tree that follows the common semantic. Then, the in-memory description can be subject to different user-defined manipulations built on top of a series of API or visitor/listener classes. Finally, the description goes through the desired back-end, transforming the in-memory description into the target transistor-level language. As a use-case for the proposed framework, we chose the process of analog fault injection. This activity requires adding, removing, or replacing nodes, components, or even entire sub-circuits. Therefore, the framework is completely written in C++, and its APIs are also interfaced with python. The entire framework is open-source and available on GitHub.