The technology scaling has boosted the importance and gravity of radiation faults. Hardening techniques are required to ensure a high level of reliability, mainly to the harsh critical applications. Hardware redundancy remains the most adopted option to deal with fault tolerance, mostly the TMR technique. However, the weakness of this technique is the voter circuit. This paper investigates the robustness of nineteen majority voter designs in the presence of a SET. The analysis explores critical diffusion areas and LET threshold. The results show designs with 3X difference in the number of critical diffusion areas and 6X in the LET threshold.

The aggressive technology scaling has significantly affected the circuit reliability. Several techniques have been explored to mitigate the scaling effects and guarantee a satisfactory reliability level. In this context, estimating circuit reliability is crucial and a challenge that has not yet been overcome. For decades, traditional reliability estimation techniques have used fixed logic gates reliability values. Recently, methods demonstrate that using fixed gate reliability values compromises the accuracy of the analysis. This work evaluates the impact of the estimated logic gate susceptibility in the reliability of several benchmarks circuits mapped with different sets of logic gates. The obtained results show a discrepancy in the reliability of the same circuit. However, the change in the reliability behavior may be considered the main contribution of this work. The utilization of fixed reliability values for logic gates provides reliability values inversely proportional to the number of gates in the circuit. The used approach captures the logical characteristics of the gates. The same circuit mapped with basic gates presents a difference in MTBF of 20%, while the one mapped with a complex set of gates is bigger than 70%.