The article considers a large class of delayed neural networks (NNs) with extended memristors obeying the Stanford model. This is a widely used and popular model that accurately describes the switching dynamics of real nonvolatile memristor devices implemented in nanotechnology. The article studies via the Lyapunov method complete stability (CS), i.e., convergence of trajectories in the presence of multiple equilibrium points (EPs), for delayed NNs with Stanford memristors. The obtained conditions for CS are robust with respect to variations of the interconnections and they hold for any value of the concentrated delay. Moreover, they can be checked either numerically, via a linear matrix inequality (LMI), or analytically, via the concept of Lyapunov diagonally stable (LDS) matrices. The conditions ensure that at the end of the transient capacitor voltages and NN power vanish. In turn, this leads to advantages in terms of power consumption. This notwithstanding, the nonvolatile memristors can retain the result of computation in accordance with the in-memory computing principle. The results are verified and illustrated via numerical simulations. From a methodological viewpoint, the article faces new challenges to prove CS since due to the presence of nonvolatile memristors the NNs possess a continuum of nonisolated EPs. Also, for physical reasons, the memristor state variables are constrained to lie in some given intervals so that the dynamics of the NNs need to be modeled via a class of differential inclusions named differential variational inequalities.

We have proposed a digital frequency measurement technique with enhanced accuracy, exploiting FPGA Mixed-Mode Clock Management for QCM-D technology. In detail, the method is based on the multi-phase generalization of the basic direct period measurement technique, involving low-complexity digital architectures based on gated counters. Theoretical analysis has been validated by experimental results, referring to a design implemented on a Xilinx Artix-7 FPGA. The proposed solution allowed to reach a worst-case frequency measurement error of ≈ 20Hz for an observation period of$200\mu \mathrm{s}$of a damped QCM sensor resonating at 10MHz.

We discuss a novel investigation approach to study current limiting techniques for accurate memristor programming. In detail, referring to the case of the Stanford memristor model, we propose to analyze its programming dynamics adopting a nonlinear static analysis point of view and considering, for the sake of simplicity, the special case of a linear resistive current limiter.

We discuss a monitoring system aiming to select, among a set of integrated entropy sources affected by process variability, the source guarantying the highest worst-case entropy. The approach is particularly suitable when considering True Random Number Generators based on Digital Nonlinear Oscillators, since multiple instances of the entropy sources can be implemented at a reduced hardware cost. In general, the approach can be applied for TRNGs based on parametric systems, thus offering entropy tuning capabilities. The original theoretical results have been validated with experiments.

Controlling multistability, i.e., designing control laws for switching among different attractors, is an emerging issue in the area of memristor circuits. The paper considers the Chua’s memristor circuit which is known to display infinitely many attractors, each one contained in an invariant manifold of the circuit state space. The problem of switching among these attractors via pulse-programmed feedforward control laws, which are implementable via a unique current/voltage source, is investigated. In particular, it is shown that if the shape of the voltage source in series to the inductor is suitably designed, then it is possible to switch in finite time from one attractor to another.

We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication.

We propose a novel class of Digital Nonlinear Oscillators (DNOs) supporting complex dynamics, including chaos, suitable for the definition of high-performance and low-complexity entropy sources in digital programmable devices. We derive our solution from the analysis of simplified models, proposing a low-complexity `fully digital' chaotic entropy source consuming few look-up tables in a Xilinx FPGA. The validity of the proposal has been verified with experiments.

We investigate and compare three low complexity circuit topologies to be implemented in programmable logic devices, for the design of True Random Bit Generators for Lightweight Cryptography. The architectures, based on the general idea of Digital Nonlinear Oscillators (DNOs), have been compared on the basis of measurement campaigns, carried out referring to figures of merit specifically introduced to assess the quality and reliability of the oscillators under test.

We present a novel approach for guaranteeing access privacy to data stored at an external cloud provider. Our solution relies on the grouping of resources into buckets then organized with a binary search tree. The tree is built on an index computed in a non-invertible non-order preserving way, and supports efficient key-based retrieval. Our approach to provide access privacy builds on this data organization providing uniform observability to the server in access execution and dynamically changing not only the physical storage allocation, but also the logical structure itself. Our analysis and experimental evaluation show the effectiveness of our approach.