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Daniel Rozhko

dblp:194/3906 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 90% Memory systems · 10%
Network and information security
1 paper
Network security · 100%

Topics — the 2 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
datacenter FPGA deployment
0.112019
The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs · FPGA 2019
Memory systems › 3d-stacked memory
hybrid memory cube
0.112017
Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules · FPGA 2017

Methods — techniques the papers use, named apart from their topics

switch-level management offload · 0.8hairpin routing · 0.8HMC memory integration · 0.3
YearPublicationVenuePosition
2019 The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs
abstract
Reconfigurable compute devices, namely Field Programmable Gate Arrays (FPGA), have increasingly been deployed in datacenters and cloud infrastructures. Such devices have proven effective at performing certain types of compute tasks, often performing these tasks faster, with lower latency, at a higher throughput, and/or at lower power than traditional compute devices (e.g. CPUs). Some recent works have demonstrated the benefits of deploying such devices as direct-connected nodes, i.e., the FPGAs are connected directly to the datacenters' network infrastructure. In this work, we introduce the concept of the Network Management Unit (NMU), which secures the network from potentially unwarranted access from malicious or malfunctioning FPGA applications; specifically, the NMU targets network traffic originating from (or targeted towards) an application resident solely on the FPGA itself. We argue that this is a necessary feature of direct-connected reconfigurable compute devices. We present the design of several NMUs, introduce a taxonomy for describing these different designs, and analyze the trade-offs of each design. The NMUs discussed range from those that employ hairpin routing techniques to push management to the next level switch, to those that perform routing and access control directly.
Daniel Rozhko, Paul Chow
FPGA1
2017 Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules
Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen
FPGA1