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Daniel Ly-Ma

dblp:194/3963 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 54% Cloud and datacenter computing · 30% High-performance computing · 9%

Topics — the 2 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › cluster computing
cluster deployment
0.112019
A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center · FPGA 2019
Memory systems › 3d-stacked memory
hybrid memory cube
0.112017
Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules · FPGA 2017

Methods — techniques the papers use, named apart from their topics

high-level synthesis · 0.4HMC memory integration · 0.3
YearPublicationVenuePosition
2019 A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center
abstract
In this work we present a heterogeneous deployment stack, calledGalapagos, that includes the abstraction of individual nodes (FPGAsand CPUs), the communication protocols between nodes and theorchestration and connection of these nodes into clusters. The stackwe create is also highly modular, allowing users to explore a designspace in the implementation of their cluster such as different net-work protocols or communication layers. The communication layerwe have currently implemented within our hardware stack, calledHUMboldt, handles heterogeneous communication between multi-ple FPGAs and CPUs. We implementHUMboldtusing High-LevelSynthesis (HLS) to ensure functional portability of communicatingkernels, allowing us to prototype hardware kernels in software. Ourresults have shown that our modular approach to this heterogeneousdeployment stack has introduced very little area and latency over-head in the FPGAs and can still perform at line-rate, bottleneckedsolely by the network links connecting the nodes. Our results alsohighlight the scalability of our design as our performance remainslimited by the network links when the cluster size increases.
Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow
FPGA3
2017 Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules
Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen
FPGA3