3D multi-object visual grounding aims to identify and localize all objects in a 3D scene that correspond to a given text description. Unlike traditional single-object grounding, this task presents additional challenges as point clouds inherently lack fine-grained details, making it difficult to capture subtle object features and contextual information. Moreover, textual descriptions are inherently limited in perceiving and understanding complex 3D environments, especially in scenarios with high object similarity or intricate spatial arrangements. To tackle the above challenges, we propose SGMG, a Rendered 2D Semantic and Generative priors guided 3D Multi-object Grounding Framework. The SGMG framework introduces two key innovations that work cohesively to enhance grounding accuracy. First, a Generative-Assistant(GA) Module leverages the capabilities of a generative model to provide enriched scene prior information and capture the fine-grained scene details. Second, the Semantic-Augment Fusion(SAF) Module is designed to improve the representation of text features from the vision features, thereby boosting the accuracy of multimodal information interactions. Furthermore, we introduce a multi-level fusion mechanism, ensuring that semantic and spatial relationships between objects are preserved and effectively leveraged during the grounding process. Experimental results demonstrate that SGMG achieves state-of-the-art performance in multi-object 3D grounding and competitive results in traditional single-object tasks, highlighting its effectiveness in diverse scenarios.

This paper proposes a 1.5 GS/s 9-bit two-stage pipelined SAR analog-to-digital converter (ADC) in 28 nm CMOS. Simultaneously with amplification, the inter-stage residue is converted to time-domain (TD) and quantized by a TDC. This results in significant resolution improvement of the second stage under the speed of 1.5 GS/s. A double-edge quantized TDC with improved time resolution is proposed for higher conversion speed in the time domain and less power consumption. Moreover, a cascode switching inverter-based open-loop amplifier is proposed featuring low gain error, fast settling, and low power. With a sampling speed of 1.5 GS/s, the simulation results show that the ADC achieves 55 dB SNDR and 66.7 dB SFDR at the Nyquist frequency and 1-Vppinput swing, while the power consumption is 6.86 mW, yielding a Walden FoM of 10.2 fJ/con-step.

Long user history is highly valuable signal for recommendation systems, but effectively incorporating it often comes with high cost in terms of data center power consumption and GPU. In this work, we chose offline embedding over end-to-end sequence length optimization methods to enable extremely long user sequence modeling as a cost-effective solution, and propose a new user embedding learning strategy, multi-slicing and summarization, that generates highly generalizable user representation of user's long-term stable interest. History length we encoded in this embedding is up to 70,000 and on average 40,000. This embedding, named as DV365, is proven highly incremental on top of advanced attentive user sequence models deployed in Instagram. Produced by a single upstream foundational model, it is launched in 15 different models across Instagram and Threads with significant impact, and has been production battle-proven for >1 year since our first launch.

This article presents a single-channel 4-GS/s 8-bit hybrid-domain analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. The proposed 8-bit ADC combines a 3-bit voltage-domain stage with a 6-bit time-domain (TD) backend to take full advantage of the voltage and time domains. A high-speed hybrid-loop residue amplifier (RA) is proposed with a settling time of less than 150 ps, while a non-symmetrical pipeline timing utilizing a 25% duty cycle clock is used to increase the TD quantization time and the settling time margin of the RA. A low-power and small-area gated-ring-oscillator-based TD backend is employed, which operates at 4-GS/s with 6-bit resolution. The prototype hybrid ADC occupies an active area of 0.0114 mm2. Under a 1-V power supply and Nyquist input, the chip achieves a measured ENOB of 6.46 bits at a conversion rate of 4 GS/s, while the power consumption is 10.6 mW and the FoMw is 29.9 fJ/conversion-step.

With the increasing role of social media in information dissemination, effectively simulating and analyzing public event dynamics has become a key research focus. We present an interactive visual analysis system for simulating social media events using multi-agent models powered by large language models (LLMs). By modeling agents with diverse characteristics, the system explores how agents perceive information, adjust their emotions and stances, provide feedback, and influence the trajectory of events. The system integrates real-time interactive simulation with multi-perspective visualization, enabling users to investigate event trajectories and key influencing factors under varied configurations. Theoretical work standardizes agent attributes and interaction mechanisms, supporting realistic simulation of social media behaviors. Evaluation through indicators and case studies demonstrates the system’s effectiveness and adaptability, offering a novel tool for public event analysis across open social platforms.

Beam tracking is an essential procedure in millimeter Wave (mmWave) communication systems for providing reliable and robust service. However, beam tracking is a challenging task due to dynamically unpredictable channels. In this paper, we propose a Channel Charting (CC) based beam tracking algorithm to provide robust communication service with low beam search complexity. By projecting the beam direction information to the beam feature domains, the beam tracking problem is transformed into the search of the beam cluster in the beam feature domains. Since the channel chart enables clustering of high-dimension Angles of Arrival (AoA) and Angles of Departure (AoD) to low-dimension beam domains regardless of geographic location, the search complexity is significantly reduced. Furthermore, the neighborhood search algorithm can be applied to obtain the optimal features. The proposed method reduces the search times about 50% in simulation work, with the average tracking accuracy of 98.27%. We also perform the field tests, the results show a high similarity to the simulation. The proposed method exhibits low search complexity with high tracking accuracy in the real scenario.

Global routing has become more challenging due to advancements in the technology node and the ever-increasing size of chips. Global routing needs to generate routing guides such that (1) routability of detailed routing is considered and (2) the routing is deterministic and fast. In this paper, we firstly introduce soft capacity which reserves routing space for detailed routing based on the pin density and Rectangular Uniform wire Density (RUDY). Second, we propose a deterministic parallelization approach that partitions the netlist into batches and then bulk-synchronously maze-routes a single batch of nets. The advantage of this approach is that it guarantees determinacy without requiring the nets running in parallel to be disjoint, thus guaranteeing scalability. We then design a scheduler that mitigates the load imbalance and livelock issues in this bulk synchronous execution model. We implement SPRoute 2.0 with the proposed methodology. The experimental results show that SPRoute 2.0 generates good quality of results with 43% fewer shorts, 14% fewer DRCs and a 7.4X speedup over a state-of-the-art global router on the ICCAD2019 contest benchmarks.

The increasing control complexity of Noisy Intermediate-Scale Quantum (NISQ) systems underlines the necessity of integrating quantum hardware with quantum software. While mapping heterogeneous quantum-classical computing (HQCC) algorithms to NISQ hardware for execution, we observed a few dissatisfactions in quantum programming languages (QPLs), including difficult mapping to hardware, limited expressiveness, and counter-intuitive code. In addition, noisy qubits require repeatedly performed quantum experiments, which explicitly operate low-level configurations, such as pulses and timing of operations. This requirement is beyond the scope or capability of most existing QPLs. We summarize three execution models to depict the quantum-classical interaction of existing QPLs. Based on the refined HQCC model, we propose the Quingo framework to integrate and manage quantum-classical software and hardware to provide the programmability over HQCC applications and map them to NISQ hardware. We propose a six-phase quantum program life-cycle model matching the refined HQCC model, which is implemented by a runtime system. We also propose the Quingo programming language, an external domain-specific language highlighting timer-based timing control and opaque operation definition, which can be used to describe quantum experiments. We believe the Quingo framework could contribute to the clarification of key techniques in the design of future HQCC systems.

Asynchronous Very-Large-Scale-Integration (VLSI) has several potential benefits over its synchronous counterparts, such as reduced power consumption, elastic pipelining, and robustness to variations. However, the lack of electronic design automation (EDA) support for asynchronous circuits, especially physical layout automation tools, largely limits their adoption. To tackle this challenge, we propose a gridded cell layout methodology for asynchronous circuits, in which the cell height and cell width can be any integer multiple of two grid values. The gridded cell approach combines the shape regularity of standard cells with the size flexibility of custom design, and thus achieves a better space utilization ratio and lower wire-length for asynchronous designs. We present the algorithms and our implementation of Dali, a gridded cell placer, that consists of an analytical global placer, a forward-backward legalizer, an N/P-well legalizer, and a power grid router. We show that the gridded cell placement approach reduces area by 15% without impacting the routability of the design. We have also used Dali to tape out a chip in a 65nm process technology, demonstrating that our placer generates design-rule clean placement.