A cryogenic complementary metal-oxide semiconductor (cryo-CMOS) ultra-high-frequency (UHF) analog filter designed for enabling scalable quantum control interfaces is presented in this work. Effective filtering at both analog-to-digital and digital-to-analog conversion stages is critical to maintain signal integrity and achieve high-fidelity qubit control and readout. The proposed filter employs a differential flipped-voltage-follower-based topology, facilitating compact single-branch design, high linearity, and low power consumption. An on-chip buffer stage and a de-embedding technique for precise chip measurements are also presented. The filter is designed using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FD-SOI) technology, leveraging a low-voltage operation of 0.8 V, facilitating low power consumption. A key advantage of using FD-SOI technology for enabling cryogenic quantum computing hardware is the additional degree of freedom provided by the available back-gate transistor connection through which the – increased by the cryogenic (4 K) environment – threshold voltage can be restored. The filter's performance is validated through post-layout simulations, demonstrating improved performance compared to the state-of-the-art literature regarding bandwidth, linearity, and power consumption.

This brief presents a new method to characterize the linearity of on-chip filters with accurate characterization of the filter’s transfer function (TF) in both its bandpass and stopband. Unlike conventional methods, this approach uses only one buffer, simplifying the design and improving accuracy. The filter and buffer are designed using GlobalFoundries (GF) 22-nm FDX technology, incorporating a back-gate biasing tuning mechanism in the buffer design that aims to maintain the performance of the buffer under process variation. The postlayout simulations demonstrate that the new method achieves a filter linearity of$\text {IIP3}=10.46~\text {dBm}$, with an accuracy of 99.4% compared to the standalone filter’s linearity. Similar consistency is observed across process corners.

A systematic research on the development of cryogenic complementary metal-oxide semiconductor (cryo-CMOS) circuits, for implementing the required control electronics to manipulate the quantum bit (qubit) state, is performed over the last few years. Scalability constitutes a key term regarding the evolution of quantum computing from theory to practical application and CMOS technology has been proven to be a promising candidate for implementing the coveted scalable next-generation quantum computers (QCs). Mixed-signal blocks, used for uniting the analog and digital domains, play a key role in the efficient functionality of the qubit control/readout system, thus there is an ever-increasing interest in their high-performance circuit realization. The critical challenge in this venture is to achieve efficient cryogenic operation at low temperatures, i.e., close to the qubit around 4 K, simultaneously keeping power requirements at low values. An overview and comparison of the cryo-CMOS Digital-to-Analog converter (DAC) and Analog-to-Digital converter (ADC) circuit implementations for quantum computing applications that heretofore have been proposed in the literature is presented in this work. A discussion on the challenges and future strategic steps that are henceforth required to proceed toward the development of a functional scalable quantum computer is also conducted.

Fractional-order shelving filter designs, which are used for preserving the spectral balance of the human sound perception, are introduced in this work. The main attractive offered benefit is originated from the fact that fractional-order filters offer an extra degree of freedom with regards to the slope of the stop-band attenuation, allowing an improvement in the listening experience. The implementation of the filters is performed through the utilization of the partial fraction expansion of the rational integer-order transfer functions which approximate their fractional-order counterparts. The employment of Operational Transconductance Amplifiers as active elements offers the advantage of full electronic control of the implemented filters characteristics.

This paper deals with a fractional-order DC motor controller implementation, which is constructed from operational transconductance amplifiers and capacitors. In addition, for the electronic tuning capability and potential of implementation in monolithic form, the proposed structure offers significant reduction of the active components count. This is achieved through a manipulation of the transfer function of the controller integrator function in such a way that only fractional-order differentiation stage is required. An illustrative simulation example with the above mentioned benefit is presented.