The demand for advanced processing capabilities is paramount in the ever-evolving landscape of radiation-resilient computing exploration. With the standardization of vector extensions on Arm and Risc-V ISAs, leading technology companies are adopting high-performance processors to exploit vector capabilities. This work promotes uniform random fault injection techniques to assess the increased vulnerability within the adoption of vector extensions from RISC-V RVV and Arm SVE. The obtained results show the soft error criticality correlation to registers' cross-section and the vectorized benchmarks, emphasizing the necessity of performance and reliability balance in emerging devices with vector capabilities.

Machine learning (ML) algorithms offer solutions across diverse domains, including resource-constrained devices. Despite advances in performance optimization and reduced-precision implementations, ML susceptibility to soft errors from radiation remains unclear. This work uses virtual platforms (VPs) to conduct a comprehensive soft error reliability assessment, at early design phases, of ML algorithms for Arm processors. The test strategy integrates confidence metrics, extensive fault injection (FI) campaigns, application profiling, and fault classifications. The main goals comprise (i) analyzing the consistency of SOFIA, a JIT-based framework, against event-driven simulators (mean mismatch ±4%, worst-case ±8%) and (ii) investigating correlations between FI results, NN-optimized kernels, and reduced-precision CNNs for IoT devices (up to 60% critical faults), aiming to promote software-based mitigation techniques (up to 98% critical faults mitigated). Results covering over 14.8 million FIs highlight SOFIA’s consistency, offering insights into balancing performance and reliability in multithreaded IoT edge platforms.

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

Software reliability is an essential design metric in emerging large-scale multiprocessor embedded systems. Designers should identify soft error susceptibility of multiple applications executing in parallel early in the design time to ensure reliable system operation. This work proposes a non-intrusive fault injection engine that enables to conduct bespoke soft error analysis, allowing to identify and understand the soft error propagation through the processing elements (PEs). The proposed fault injection campaign evaluates the impact of soft errors considering real benchmarks in an RTL model of a distributed-memory NoC-based multiprocessor. Experiments demonstrate that 19% of soft errors are propagated to other PEs, where 31.6% of them led to erroneous computation and 58.4% to a system crash. Thus, the fault analysis must consider not only its local effect on the processor and memory but also how the fault propagates to other system components.

Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. Underlying models are traditionally meant for static scenarios where all communicating entities and their intercommunication patterns are known a priori by the software engineer. The systems design following such programming models became complex due to dynamic behavior of applications at runtime. The goal of this work is to incorporate a publish-subscribe programming model to an MPSoC framework to decouple, in the time and space, the application development. The modified MPSoC framework is composed of a FreeRTOS kernel running on homogeneous processing elements distributed into a network-on-chip. The results present reduction around of 2% to 30% in DTW application execution time, and low overhead in memory footprint when comparing the original MPI primitives with the publish-subscribe programming model.