The ability of resistive memory (ReRAM) to naturally conduct vector-matrix multiplication (VMM), the primary operation carried out in neural networks, has caught the interest of researchers. The memristor crossbar is a suitable architecture to perform VMM and additionally offers benefits like in-memory computation (IMC), low power, and high density. Memristor-based neural networks are typically trained using a mechanism where weight computations are carried out on a host machine and downloaded into the crossbar. However, due to faulty memristors in the crossbar, a cell may not be able to store the exact weight values, which may lead to inference errors. In this paper, we propose a weight-sharing method to improve the self-fault-tolerance capability of memristor crossbar. In order to reduce the impact of faulty memristors, the weights are shared among different layers of memristors in a 3D crossbar. Simulation analyses show considerable improvements in the fault-tolerance capability of the crossbar.

Memristors or Resistive Random Access Memory (RRAM) are emerging non-volatile memory devices that can be used for both storage and computing. In this type of memory the information is stored in memory cells in the form of resistance. One of the very important challenges in memristive crossbars is the existence of Sneak Paths, which result in erroneous reading of memory cells. Most of the logic in-memory techniques have emphasized on improving the logic design perspective, but have given minor importance to the sneak path issue. In this paper we show the effect of sneak paths on crossbars of various sizes, and then try to analyze the logic design approaches like MAGIC and MAJORITY with respect to their immunity to sneak paths. Experimental result shows that with some extra overhead we can eliminate the sneak path effect in various logic design methods.

Because of their resistive switching properties and ease of controlling the resistive states, memristors have been proposed in nonvolatile storage as well as logic design applications. Memristors can be fabricated in a crossbar and suitable voltages applied to the row and column nanowires to control their states. This makes it possible to move toward new non-von Neumann-type architectures, usually referred to as in-memory computing, where logic operations can be performed directly on the storage fabric. In this paper, a scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style. The memristors corresponding to the primary inputs are initialized a priori. Subsequently, the required gate operations are performed by applying suitable row and column voltages in sequence. Two alternate mapping schemes have been analyzed. The switching characteristics of MAGIC NOR gates have been evaluated using circuit simulation under the Cadence Virtuoso environment. Experimental evaluation on ISCAS'85 benchmarks reports the average improvements of 27.7%, 34.6%, and 26.2%, respectively over a recently published work with respect to the number of memristors, number of cycles, and total energy dissipation, respectively. It may be noted that the energy consumption of the gates used in the proposed approach (NOT and NOR) is significantly higher than that using CMOS technology.