Nonlinear functions are essential in signal processing, automatic control, and machine learning, serving as activation functions and enabling nonlinear space modeling. However, conventional hardware implementations, such as look-up tables (LUTs), Taylor series, and coordinate rotation digital computer (CORDIC), suffer from high overhead and limited generality. Stochastic computing (SC), a novel nonbinary computing approach, offers substantial advantages in circuit compactness and power efficiency. This article introduces a segmented multidriving multidimensional finite state machine (SMM-FSM) operator, which integrates input-space partitioning, affine normalization, and segment-specific parameter configuration to enable accurate and efficient approximation of complex and nonmonotonic univariate functions. Leveraging the Kolmogorov–Arnold (K–A) theorem, the SMM-FSM further supports multivariate nonlinear computation through the composition of univariate operators. The proposed scheme adopts a fully digital CMOS implementation, offering improved compatibility and ease of integration in practical scenarios. The results of multivariate function approximation indicate area reductions of$1.33\times $to$5.17\times $and power savings of$1.37\times $to$2.65\times $compared to traditional methods, with minimal accuracy degradation. Additionally, a knot classification circuit built using the proposed architecture significantly outperforms binary multilayer perceptron (MLP) implementations in area by$8.23 \times $, power by$3.34 \times $, and latency by$5.74 \times $, highlighting its efficiency and versatility.

Massive MIMO is a pivotal technology for 5G and beyond, significantly enhancing spectrum efficiency and system capacity by deploying numerous receiving antennas at the base station. However, the increasing number of antennas imposes strong requirements for effective interference suppression in uplink MIMO detection. While traditional MMSE-IRC provides excellent performance in mitigating interference, its computational complexity scales cubically with the number of receiving antennas, limiting its practical applicability in massive MIMO systems. This paper presents a learning-based algorithm employing Mini-batch Gradient Descent (MBGD) to solve the weight matrix of MMSE-IRC, complemented by convergence acceleration strategies that incorporate adaptive initial learning rate determination and noise-plus-interference power regularization. Convergence and robustness of the proposed algorithm are validated across diverse modulation schemes, interference levels, and antenna configurations. Performance results indicate that, under high interference conditions, the iteration count of the proposed method is merely 12.5% that of traditional MBGD, while its BER performance exceeds that of conventional MMSE-IRC by approximately 0.5 dB, achieving a reduction in complexity from$O\left(N_{r x}^{3}\right)$to$O\left(N_{t x} N_{r x}\right)$.

Multiple Input Multiple Output (MIMO) is a critical component of modern wireless communication systems, widely utilized for its enhancement of system capacity. However, one of the major challenges of MIMO is the high complexity of the detection algorithm. In this paper, we propose a novel low-complexity detection algorithm based on multi-layer perception (MLP) and stochastic gradient descent (SGD). This algorithm significantly accelerates convergence using zero-forcing initialization and momentum optimization method. Additionally, a fixed-point optimized hardware architecture is proposed. The proposed design achieves up to 2.39× higher area efficiency with respect to the existing solutions, making it a promising candidate for practical application.

By dividing Variable Nodes (VNs) into groups and processing groups sequentially, the Shuffled Min-Sum (SMS) decoding of Low-Density Parity-Check (LDPC) codes achieves a good trade-off between hardware resource and throughput. However, under the grouping strategy where at least one Check Node (CN) has multiple VN neighbors in one group, the CN update of State-Of-The-Art (SOTA) SMS decoding has long latency and high complexity. To address the issue, this paper presents two efficient CN update schemes. The first one uses the first two minimum Variable-to-Check (V2C) message magnitudes in each group and a size-λ Monotone Double-ended Queue (λMDQ), leading to an Improved λMDQ (I-λMDQ) scheme. The second one called the Modified λMDQ (M-λMDQ) scheme uses only the minimum in each group. As a result, our schemes reduce the number of Selection Modules (SMs) required by the CN update to only one. Simulation results show that both of our schemes have comparable error-correction performance to the SOTA schemes. Furthermore, we simplify the SM via a decomposition design and also present the detailed hardware architectures for our schemes. Analysis using the 90nm CMOS technology library shows that, compared to the SOTA schemes, our I-λMDQ scheme reduces the area and latency by up to 75% and 72%, respectively, while improving the throughput by up to 254%. Similarly, our M-λMDQ scheme reduces the area and latency by up to 79% and 70%, respectively, and improves the throughput by up to 229%.

Sparse code multiple access (SCMA) is a candidate technology for future wireless communication systems to enhance network access capacity. Existing multi-carrier techniques, such as orthogonal frequency division multiplexing (OFDM) that are based on SCMA schemes, are well-researched and considered promising for future 6G mobile communication networks. However, the high peak-to-average power ratio (PAPR) issue stemmed from the multi-carrier schemes limits the applications of SCMA in long-distance transmission scenarios and low-cost sensor networks. To address this issue, single-carrier based SCMA transmission scheme (SC-SCMA) with low PAPR has been proposed. However multi-user signal detection remains a significant challenge for SC-SCMA, particularly with frequency-selective channels (FSC). In this paper, we establish the self-interference analysis model of the SC-SCMA system in FSC and construct an extended factor graph (EFG) for multi-user detection. Based on that, we propose the Gaussian approximate interference based belief propagation algorithm processing on EFG (E-GAIBP) to realize efficient detection over FSC with reduced complexity. Meanwhile, an extrinsic information transfer (EXIT) chart is introduced to analyze the detection performance and convergence properties of the E-GAIBP detector. Finally, to further improve performance gains, we propose two joint E-GAIBP detection and LDPC decoding schemes, E-GAIBP-JDD and layered E-GAIBP-JDD. Numerical results and complexity evaluations show that the layered E-GAIBP-JDD excels in detection performance and convergence speed, offering an effective receiver design strategy.

As a promising contender within non-orthogonal multiple access (NOMA), sparse code multiple access (SCMA) stands out as a potential cornerstone in future-generation wireless communication systems. However, while most SCMA research assumes ideal synchronization among multiple users, the reality of non-ideal synchronization introduces multi-user access inter-ference (MAI), leading to significant performance degradation. In fact, this interference can be severe enough to cause traditional SCMA detection methods to falter in convergence. This paper delves into the theoretical analysis of MAI and introduces an innovative solution: a sample selection-based message passing algorithm (SS-MPA). The aim is to tackle this issue head-on. Through error rate performance simulations and complex-ity evaluations, our results showcase that the proposed SS-MPA algorithm, designed for asynchronous conditions, closely approaches the optimal performance of MPA in synchronous settings, all while maintaining comparable complexity levels. This breakthrough marks a significant step toward resolving MAI-related challenges in SCMA systems.

Sparse code multiple access (SCMA) is a candidate technology for further wireless communication system to enhance the multiple access capacity. The existing multi carriers technique based SCMA schemes, such as orthogonal frequency division multiplexing (OFDM), have been well studied and considered as a promising candidate for future 6G protocols. However, the high peak-to-average power ratio (PAPR) issue resulted by the multi carriers techniques limits the applications of SCMA in long distance transmission scenarios and low cost sensor networks. To address this issue, single carrier based SCMA transmission scheme (SC-SCMA) has been proposed and demonstrates low PAPR. But the multi user signal detection is still a major chal-lenge for SC-SCMA, especially for frequency selective channels (FSC). In this paper, we establish the interference model of SC-SCMA system in FSC, and construct an extended factor graph (EFG) for multi user detection. Afterward, the Gaussian approx-imate interference based belief propagation algorithm processing on EFG (E-GAIBP) is proposed, realizing efficient detection and complexity reduction. Furthermore, to earn higher performance gain, joint E-GAIBP detection and LDPC decoding scheme (E-GAIBP-JDD) is introduced. Numerical results demonstrate that compared with classical MPA using EFG, E-GAIBP shows great complexity reduction and E-GAIBP-JDD performs great performance gain.

With the rapid development of the Internet of Things (IoT), device and data security has attracted huge academic attention in recent years since conventional security methods are barely feasible in IoT circumstances. Traditional encryption methods require extensive computation complexity, which requires several hardware resources and power consumption. Meanwhile, due to the low-power requirement, most IoT devices are lightweight with limited computing and storage capabilities. The dilemma leads to the need for a lightweight encryption method with decent data protection strength. Chaotic encryption can be applied in the IoT because of the characteristics of determinacy and strong randomness. However, its safety and hardware overhead are positively correlated with implementation precision. Therefore, this article performs a quantitative analysis of the system under different precision conditions. Then, a hybrid chaotic encryption scheme with dynamic precision is proposed, which balances power consumption and security protection level. Finally, the proposed design is implemented by Verilog and synthesized using SMIC 65-nm CMOS technology. The evaluation results proved that the proposed ASIC provides decent encryption strength under diverse precision, effectively overcoming the influence of limited precision with low-hardware resources and power consumption.

With the increasing requirement for high-speed transmission, multiple input multiple out (MIMO) technologies have been proposed. Beneficial from low peak-to-average power ratio (PAPR), single carrier (SC) MIMO systems are suitable for long-distance transmission. However, one of the significant challenges of SC-MIMO systems is the vast complexity of channel equalization and signal detection, especially for the inter-symbol interference (ISI) caused by the frequency-selective fading channels. Due to acceptable complexity and near maximum likelihood (ML) detection performance, the Gaussian approximate interference (GAI) based belief propagation (BP) algorithm has attracted lots of attention. With the help of extrinsic information feedback from low-density parity check (LDPC) codes, iterative detection and decoding (IDD) scheme has been proposed, which has a near to approximate maximum a posterior (MAP) detection performance. Nevertheless, the IDD scheme still suffers from relatively slow convergence resulting from complex connections on the factor graph. Combined with the joint detection and decoding (JDD) scheme and two optimization methods, namely dynamic message damping and layered message updating, a convergence optimized joint detection and decoding (CO-JDD) algorithm is proposed in this paper. Evaluation results show that the proposed CO-JDD algorithm has 2dB bit error rate (BER) performance gains compared with IDD scheme. Besides, the proposed CO-JDD algorithm also has a 70% iteration reduction compared with the IDD scheme.

Turbo product codes (TPC) have received recent attention as a competitive forward error correction scheme in high-speed communication protocols and Extended BCH based TPC has been accepted by several optical transmission standards. Decoding complexity is one of the major challenges for TPC. This paper proposes a novel stochastic TPC decoder that processes the decoding in a bit-wise iterative manner to reduce the decoding complexity. Further, a hard-decision decoding temporary frozen strategy is proposed to further speed up the convergence and reduce the decoding complexity. The evaluation results demonstrate significant complexity reduction with error correction performance improvements compared to the existing works, making it a promising candidate for practical application.

Hybrid low-density parity-check (LDPC) decoding combines conventional Belief-Propagation (BP) algorithm with stochastic decoding to achieve high performance and low complexity simultaneously. However, lossy and inefficient stochastic-to-binary (S2B) conversion brings extra performance degradation and decoding latency. In this paper, a bit-serial stochastic updating based hybrid decoding (BSSU-HD) is proposed, which employs fully correlated stochastic (FCS) check nodes (CNs) and probability tracers assisted variable nodes (VNs) to accomplish accurate and efficient S2B conversion. Two strategies, including random source selection and tracing speed switching, are proposed to further improve performance and convergence. A BSSU LDPC decoder for IEEE 802.3an is designed in a 65-nm CMOS process, which occupies 4.6 mm2 silicon area and achieves a throughput of 200.8 Gb/s at$E_{b}/N_{0} = 4.4$dB with 500 MHz clock frequency from a 1.2 V supply voltage. The power and energy efficiency are 2.933 W and 14.61 pJ/bit, respectively. To the best of our known, it achieves the best decoding performance, the highest throughput and hardware efficiency among state-of-the-art IEEE 802.3an LDPC decoders. We also verify that the BSSU-HD can achieve better performance for multi-rate 5th generation (5G) New Ratio (NR) LDPC codes than conventional algorithm, which greatly extends the application of the stochastic decoding.

AbstractNonlinear function calculation is widely used in numerous science and technology fields. Stochastic computation is a novel high-efficiency value representation and calculation scheme for information and signal processing. The main challenges of stochastic computation based nonlinear function implementation lie on poor generalization, low accuracy and high latency. In this paper, we propose a multiple driving and multiple dimension finite state machine (MM-FSM) to realize major single variable nonlinear functions used in information and signal processing areas on common platforms with low complexity and latency. We provide corresponding synthesis method of the activation parameters and conditional parameters of MM-FSM. In order to improve the calculation accuracy, we further propose an adaptive scaling algorithm for MM-FSM. The most salient feature of MM-FSM is that we can configure different types of nonlinear functions with the same MM-FSM structure. Thus, MM-FSM can be used in a wide range of stochastic based applications. Compared with the traditional stochastic scheme and Coordinate Rotation Digital Computer (CORDIC) algorithm, simulation results show that the proposed MM-FSM nonlinear function generator has significantly lower complexity while guaranteeing the calculation accuracy.

The ultra-low hardware consumption feature of stochastic decoding has made it a potential candidate for the implementation of low-density parity-check(LDPC) decoders. However, the existing stochastic LDPC decoders still suffer from performance degradation and relatively high decoding cycles caused by the correlation among stochastic bit streams. In this paper, we propose Hybrid Stochastic(HS) decoding, which achieves high performance, high throughput, and high hardware efficiency by jointly using our proposed novel stochastic check node(CN) and Two’s Complement(TCS) variable node(VN) to realize Min-Sum Algorithm(MSA) and its enhancements. Fully correlated stochastic bit streams are used to entirely eliminate the indeterminacy caused by the correlation, which results in high performance and fast convergence and inherits the low complexity of stochastic decoders at the same time. We demonstrate the HS decoding by designing a (2048,1723) decoder in a 65 nm process, which achieves the highest Bit-Error-Ratio(BER) performance, highest throughput, and top hardware efficiency among existing stochastic LDPC decoders. We also demonstrate that HS decoding can achieve excellent decoding performance for different code rates and lengths 5G New Radio(NR) LDPC codes. Thus, HS decoding can be adopted in wide applications.

Support vector machine (SVM) is an efficient classifier for electroencephalogram (EEG) based gesture recognition whose applications usually require low hardware cost and low processing latency. Even though the training process can be unloaded to offline computing, the real-time classification process still suffers from large computing complexity, making it difficult to implement on wearable devices. Stochastic computing is a promising low hardware cost and low power consumption implementation candidate. In this paper, a novel stochastic computing based SVM classifier is proposed for real-time EEG based gesture recognition to reduce the hardware cost. Besides, to overcome the long latency drawback of stochastic computing, a parallelism optimization method is utilized in the proposed design. According to the evaluation results, the proposed stochastic SVM classifier significantly outperforms the existing binary schemes on hardware cost and achieves comparable classification accuracy with float-point performance.

Healthcare demands of a worldwide aging population is increasing at an alarming rate. However, current medical and healthcare systems are unable to meet with the increased demands and are in danger of failing to deliver a much needed respite. With rapid progress in telecommunication technology, development of Wireless Body Networks has emerged as a feasible solution to address such urgent healthcare demands. Although these networks are able to provide real-time health condition monitoring, its adoption and acceptance are still very low. This is due in part to the high power requirement of current networks as well as security concerns in the transmission of personal medical data. To address those concerns, we delivered an low power ASIC solution which is implemented using SMIC 40nm CMOS technology. In this paper, we evaluated the performance of the chip in terms of its low power consumption, low latency and steady performance.

In recent years, data security becomes a critical issue restricting the wider acceptance of Internet of Things (IoT) devices and Cyber-physical systems since they have limited hardware resources and power supply while high data security protection requires relatively large hardware resources and power supply utilization. This contradiction is particularly prominent in the field of Wireless Body Area Networks (WBANs) which is a segment of the IoT field. WBANs are dedicated to transmit and process biomedical data collected from human beings, any kind of tampering or hacking may cause severe consequences to users. However, the limited computing ability and battery supply of biomedical sensors attached or implanted in the users restrict the security protection strength of the data in WBANs. In this paper, a quantized Logistic mapping-based stream encryption scheme for WBANs is proposed. Meanwhile, Power spectral entropy (PSD) and Peak-to-average Power Ratio (PAPR) analysis of the quantized chaotic sequences have been performed to evaluate the chaotic characteristic among different quantization precision to resolve the ineffectiveness of Lyapunov factor in quantized systems. This encryption scheme utilizes chaotic systems with different quantization precision based on the security requirement of every individual communication, which leads to higher hardware and power efficiency. Finally, the proposed encryption scheme is implemented with VHDL and synthesized using SMIC 60 CMOS technology. The evaluation results illustrate that the proposed encryption scheme has the advantages of high-security performance and high-efficiency hardware resources utilization.

Sparse code multiple access (SCMA) is one of the promising non-orthogonal multiple access (NOMA) techniques for the future wireless communication systems, which can provide more connections and higher spectral efficiency than orthogonal multiple access (OMA). In this paper, we propose a novel expectation propagation algorithm based on approximate computing to achieve low complexity and high performance SCMA detection, which is referred as approximate expectation propagation algorithm (AEPA). Three approximate approaches are provided for variable node update, function node update and log likelihood ratio calculation to reduce the algorithm complexity. The parameter optimization methods are also provided to get the trade-off between the detection performance and the algorithm complexity. Simulation and evaluation results show that AEPA can obtain more than 32% complexity reduction with only 0.1dB performance loss when the codebook size is 4 compared with the traditional expectation propagation algorithm (EPA), and the complexity reduction gain will become more significant when the codebook size is larger.

The increasing demand for wireless data transmission between wearable health care devices and central processing equipment has caused a consequential growth in the need for effective and reliable wireless body area network solution. The latest international standard, IEEE 802.15.6-2012 specifies the characteristics of the physical layer (PHY), multiple access control (MAC) layer, and security scheme. However, the system-level testbed gradually becomes a great challenge for the development of WBAN systems compared with other prevailing communication protocols such as Bluetooth and Zigbee. In this paper, we introduce a Software Defined Radio(SDR) based Testbed for WBAN. Benefiting from the rapid prototyping nature of the SDR platform, this testbed is shown to provide a solid testing environment for WBAN developers, as well as good testbed candidate for the future updated protocols.

Polar codes have received recent attention due to their potential to be applied in advanced wireless communication protocols such as the fifth generation mobile communication system (5G). Among the existing decoding algorithms, Belief Propagation (BP) exhibits high-throughput, low-latency and soft output with a high hardware cost. A form of approximate computing called stochastic computing provides a low-cost implementation solution for the BP algorithm. However, existing stochastic BP decoders suffer from a relatively long decoding latency resulting in low hardware efficiency. In this paper, a novel bit-wise iterative stochastic decoding architecture for the BP algorithm is proposed to improve the throughput and hardware efficiency. Multiple methods at the algorithm and architecture levels are presented to further speed up convergence and hardware efficiency.

Body Area Networks (BAN) have caused wide interest in academic and industrial areas in recent years due to the strong demands of health condition monitoring by people. Consequently, security becomes a critical consideration, which restricts the development of BAN while the data transferring in BAN is increasingly significant and their privacy is of the utmost importance. Therefore, an ASIC implementation of security scheme for BAN is proposed by the authors, based on the IEEE standard 802.15.6, which is synthesized using the SIMC 65nm CMOS technology.