Demo Data from EDBT 2026 / reviewers in the wild / expert
Shang-Feng Wu
dblp:195/1521
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 61% Processor architecture and microarchitecture · 30% Electronic design automation · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
chip multiprocessor |
0.3 | 1 | 2017 | Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips · IEEE Trans. Parallel Distributed Syst. 2017 |
Parallel and multicore computing › task scheduling
communication-aware scheduling |
0.3 | 1 | 2017 | Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips · IEEE Trans. Parallel Distributed Syst. 2017 |
Parallel and multicore computing
task scheduling |
0.3 | 1 | 2017 | Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips · IEEE Trans. Parallel Distributed Syst. 2017 |
Electronic design automation
design optimization |
0.1 | 1 | 2017 | Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips · IEEE Trans. Parallel Distributed Syst. 2017 |
Methods — techniques the papers use, named apart from their topics
task duplication · 0.3integer linear programming · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-ChipsabstractMany applications such as streaming applications are both computation and communication intensive. The Multi-Processor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) outperforms the multiprocessors with bus-based networking architecture in communication bandwidth and scalability, making it a better choice for implementing systems running these applications. It's important to schedule both the computation and communication onto processors and the networking architecture so as to satisfy the stringent timing requirements. To reduce or avoid inter-processor communication, task duplication has been employed in scheduling. Most of the available techniques for the duplication-based scheduling problem use heuristics to solve the problem, and seldom has any work studied further improving the schedule performance, despite the fact that the heuristic cannot provide quality guarantee. To fill in this gap, this paper introduces a duplication and mapping constrained task-communication co-scheduling problem that assumes the duplication strategy and task-to-processor mapping are known a priory, and proposes two Integer Linear Programming (ILP) formulations, i.e., CF-ILP and CA-ILP, to solve two editions of this problem, i.e., the contention-free problem and the contention-aware problem. The proposed ILP formulations optimize the ordering and timing of the communication and computation, thus improving the performance. Both synthesized and real applications are tested on a set of platforms to evaluate the performance of the proposed methods. The experimental results demonstrate the effectiveness of the proposed methods. Qi Tang 0002, Shang-Feng Wu, Jun-Wu Shi, Jibo Wei |
IEEE Trans. Parallel Distributed Syst. | 2 |