Photoacoustic (PA) imaging technology integrates the deep penetration depth of ultrasound imaging with the high resolution of optical imaging, demonstrating significant potential in biomedical applications. Many preclinical studies and clinical applications urgently require a portable, high-quality, low-cost, and fast imaging system. Thus, translating advanced image reconstruction algorithms into hardware implementations is highly desired. However, existing iterative PA image reconstructions, although exhibit higher accuracy than the delay-and-sum algorithm, suffer from high computational cost. In this paper, we introduce a novel model-based hardware architecture for palm-size PA tomography (palm-PAT), aiming at enhancing both the speed and performance of image reconstruction at a much lower system cost. To achieve this, we propose an innovative data reuse method that significantly reduces the consumption of hardware storage resources, achieving a reduction of approximately 75% in hardware storage requirements. We conducted experiments utilizing the FPGA implementation of the algorithm, using phantom, human finger data in vivo and ex vivo breast tumor data to verify the feasibility of the proposed method. The results demonstrate that our proposed architecture can substantially reduce system cost while maintaining high imaging performance. The novel hardware architecture design of the model-based algorithm achieves a speedup of up to approximately 270 times compared to the CPU, while the corresponding energy efficiency ratio is improved by more than 2700 times.

This paper proposes an input range boosting technique for successive-approximation-register (SAR) analog-to-digital converters (ADC). By performing a pre-comparison and switching the DAC accordingly, the input range of a SAR ADC can be doubled with limited power and area overhead. This effectively improves the power efficiency by relaxing the noise requirement and improves the area efficiency by using less DAC capacitors. A prototype ADC is fabricated in 65 nm CMOS and occupies an area of 0.0033 mm2. It consumes$34.06\ \mu\mathrm{W}$at 10 MHz sampling rate from a 1 V supply. The measured SNDR is 62 dB for a 5 MHz bandwidth, resulting in a Walden figure of merit ($\text{FoM}_{W}$) of 3.28 fJ/conversion step.

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of $32 \mu \mathrm{W}$. The estimated area is 0.002 mm2including decoupling capacitors.

Three-phase VIENNA rectifier with carrier-based pulse-width modulation (CBPWM) is widely used in various fields for its simple structure and high reliability. However, continuous high switching frequency of very semiconductors leads to considerable switching losses. The carrier-based discontinuous modulation (CB-DPWM) method is a preferable method to avoid the switching losses and achieve high efficiency. However, it results in extra issues around the zero-crossing area, causing current distortion. Therefore, a compensation strategy is deployed to address this problem. Moreover, a retrofit zero sequence component injection method is proposed to enhance the neutral-point potential balance ability of the CB-DPWM method. The feasibility of the employed methods are verified by simulation.