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Peikun Wang

dblp:195/3003 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2020
0000-0001-6625-7499ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault modeling
0.412020
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation
hardware verification and test
0.412020
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › hardware verification and test › fault modeling
multiple stuck-at fault
0.412020
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › hardware verification and test
test generation
0.412020
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

incremental test pattern generation · 0.4
YearPublicationVenuePosition
2020 An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns
abstract
As the number of transistors in the fabricated circuits becomes extremely larger, not only single stuck-at faults, but also multiple stuck-at faults (MSAFs) are likely to happen in the circuits, especially for the large-scale circuit. Multiple faults are difficult to be fully covered due to the exponentially enormous number of all possible faults. Although there are methods proposed to deal with the multiple faults, they fail to generate compact test patterns to detect all faults within an acceptable running time. In order to solve these problems, this article proposes an incremental automatic test pattern generation method to deal with MSAFs. Instead of traversing the entire n multiple fault list, the proposed method only selects the faults undetected by the existing test patterns for n - 1 faults, and then generates additional test patterns. Staring from a complete test set for single faults, the proposed ATPG method can be incrementally applied to handle all multiple faults. Moreover, since the number of undetected faults that are selected is extremely smaller comparing to the total number of the entire fault list, the proposed method can generate compact test patterns to cover all faults within an acceptable running time.
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita 0004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2019 An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults
abstract
This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set for n multiple faults, only the additional test patterns for the undetected faults by the existing test patterns for n - 1 multiple faults are generated. Moreover, by introducing an efficient fault selection method, the size of the fault list to be dealt with is reduced drastically compared to the entire fault list of n multiple faults. Our experimental results on ISCAS 89 and IWLS 2005 benchmarks up to triple faults indicate that the proposed method can generate a compact test set to cover all the faults within an acceptable runtime.
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita 0004
VTS1
2017 Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults
abstract
Previous works have shown that given an initial set of test patterns for single faults, relatively few additional tests are required to cover all multiple faults. In this paper, the exact situations in which the test patterns for single stuck-at faults do not detect multiple stuck-at faults are examined. We present proofs which show the conditions that is required to be met for ATPG on single faults to cover all multiple faults. Based on this analysis, we propose a new incremental ATPG method which first targets only single faults and then incrementally expands it to multiple faults with larger cardinalities, and present the experimental results for double faults.
Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita 0004
ISCAS2