Stochastic computing (SC) is a reemerging computing paradigm that offers low-cost and noise-resilient hardware designs for a variety of arithmetic functions. In SC, circuits operate on uniform bit-streams, where the value is encoded by the probability of observing ‘1’s in the stream. The accuracy of SC operations highly depends on the correlation between input bit-streams. Some operations, such as minimum and maximum, require highly correlated inputs, whereas others like multiplication demand uncorrelated or statistically independent inputs for accurate results. Developing low-cost and accurate correlation manipulation circuits is critical, as they allow correlation management without incurring the high cost of bit-stream regeneration. This work introduces novel in-streamcorrelatoranddecorrelatorcircuits capable of: 1) adjusting correlation between stochastic bit-streams and 2) controlling the distribution of ‘1’s in the output bit-streams. Compared to state-of-the-art (SoA) approaches, our designs offer improved accuracy and reduced hardware overhead. The output bit-streams enjoylow-discrepancy (LD)distribution, leading to higher quality of results. To further increase the accuracy when dealing with pseudo-random inputs, we propose an enhancement module that balances the number of ‘1’s across adjacent input segments. We show the effectiveness of the proposed techniques through two application case studies: SC design of sorting and median filtering.

Low-discrepancy (LD) bit-streams have been proposed to improve the accuracy and computation speed of stochastic computing (SC) circuits. These bit-streams are conventionally generated by using a quasi-random number generator such as a Sobol sequence generator and a comparator. The high hardware cost of such number generators makes the current comparator-based generators expensive in terms of area and power cost. The hardware cost issue further aggravates when increasing the number of inputs and the precision of data. A finite state machine (FSM)-based LD bit-stream generator was proposed recently to mitigate this hardware cost. The proposed generator, however, can only generate a specific LD pattern and hence, cannot be used where multiple independent LD bit-streams are needed. In this work, we propose a low-cost FSM-based LD bit-stream generator that supports generation of any number of independent LD bit-streams. The proposed generator reduces the hardware area and the area-delay product up to 80 % compared to those of the state-of-the-art comparator-based LD bit-stream generator while generating accurate bit-streams. We develop a parallel design of the proposed generator and show that the 8 × parallel implementation reduces the hardware cost on average more than 82 percent compared to the cost of the state-of-the-art parallel LD generator. Taking advantage of the provided area saving we improve the fault tolerance of the bit-stream generation unit, a vulnerable component in SC systems, by orders of magnitude. We show the effectiveness of using the proposed generator in SC-based design of convolution function as the case study.

Stochastic computing (SC) is a re-emerging computing paradigm providing low-cost and noise-tolerant designs for a wide range of arithmetic operations. SC circuits operate on uniform bit-streams with the value determined by the probability of observing 1's in the bit-stream. The accuracy of SC operations highly depends on the correlation between input bit-streams. While some operations such as minimum and maximum value functions require highly correlated inputs, some other such as multiplication operation need uncorrelated or independent inputs for accurate computation. Developing low-cost and accurate correlation manipulation circuits is an important research in SC as these circuits can manage correlation between bit-streams without expensive bit-stream regeneration. This work proposes a novel in-stream correlator and decorrelator circuit that manages 1) correlation between stochastic bit-streams, and 2) distribution of 1's in the output bit-streams. Compared to state-of-the-art solutions, our designs achieve lower hardware cost and higher accuracy. The output bit-streams enjoy a low-discrepancy distribution of bits which leads to higher quality of results. The effectiveness of the proposed circuits is shown with two case studies: SC design of sorting and median filtering.

Low-discrepancy (LD) bit-streams have been proposed to improve accuracy and computation speed of stochastic computing (SC) circuits. These bit-streams are conventionally generated using a quasi-random number generator such as a Sobol sequence generator and a comparator. The high hardware cost of quasi-random number generators makes the current comparator-based LD bit-stream generators expensive in terms of area and power cost. The hardware cost issue further aggravates when increasing the number of inputs and the precision of data. A finite state machine (FSM)-based LD bit-stream generator was proposed recently to mitigate this hardware cost. The proposed generator however can only generate one LD pattern which limits its application to SC circuits with only one LD bit-stream. This work proposes LDFSM, a low-cost FSM-based LD bit-stream generator that supports generation of any LD pattern. LDFSM reduces the hardware area and the area-delay product up to 80% compared to those of the state-of-the-art LD bit-stream generator.

Deterministic approaches to stochastic computing were proposed recently to produce completely accurate results with stochastic logic. Real-valued numbers in the [0,1] interval are converted to unary or pseudo-random bit-streams and processed using the relatively prime bit-stream length, clock division, or rotation method. Fast converging deterministic methods based on low-discrepancy bit-streams were also introduced. Long latency is the main issue with all these deterministic methods. To process m n-bit precision numbers, bit-streams of 2(m*n) bits must be generated. In this work, we propose a context-aware bit-stream generator to improve the performance of the deterministic bit-stream processing systems. The proposed design reduces the processing time up to 86% for the cases that completely accurate results are desired. When the application can tolerate some small rates of inaccuracy orders of magnitude reduction in the latency are achievable.

Deterministic methods of processing bit-streams have been proposed to produce completely accurate results with stochastic logic. Long latency is the main issue with these methods. To process m n-bit precision numbers, bit-streams of 2^m×n) bits must be generated. In this work, we propose a context-aware bit-stream generator that improves the performance of these deterministic methods.

With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to improve the endurance of NVM-based caches by reducing the activity of frequent data patterns. Simulation results show that WIPE improves the endurance by up to 93% with negligible overheads.