With the advancement of complementary metal–oxide–semiconductor (CMOS) technologies, layout-dependent effects (LDEs) become increasingly influential to MOSFET characteristics and in turn analog integrated circuit performance. Early awareness of LDEs before the layout stage gets critical in order to help subsequent layout synthesis meet performance requirements and thus reduce design iteration. In this article, we propose a high-dimensional many-objective Bayesian optimization (HMBO)-based LDE-aware sizing methodology to address such challenges. It can effectively tackle the huge configuration space that is incurred by the increased number of optimization variables for considering the LDEs in addition to the conventional sizing variables. Moreover, our proposed method is able to aim for simultaneously satisfying multiple circuit specifications to identify an optimum design point within the enlarged configuration space. In addition, we propose a performance-driven pattern learning scheme called Gibbs-upper confidence bound (UCB) for better managing the dimension splitting. Our method is compared with several prevalent evolutionary algorithms as well as state-of-the-art Bayesian optimization works designed for analog circuit sizing problems. The experimental results demonstrate the high efficacy of our proposed sizing methodology.

Layout-dependent effects (LDEs) have become increasingly more important in the synthesis of analog integrated circuits. In this article, a two-phase hybrid sizing method for high-performance analog circuits is proposed. It consists of gm/ ID-based device characterization, circuit modeling, sensitivity-based constraints for LDEs, mixed-integer nonlinear programming (MINLP) in the first phase, and many-objective evolutionary algorithm (many-OEA)-based sizing in the second phase. In the first phase, accurate device characterization is handled with little modeling effort thanks to the gm/ IDdesign methodology. Then, the LDE parameters that are linked to the normalized dc current are further optimized with the aid of sensitivity analysis. Thus, a variety of electrical, geometrical, and LDE-related constraints can be conveniently integrated into modeling of the sizing problem. In the second phase, the many-OEA-based sizing refiner can further optimize the LDE parameters by using more detailed layout information via our proposed model. A new floorplan variation scheme is also applied to improve computation efficiency and enhance optimization effectiveness. The experimental results demonstrate high efficacy of our proposed methodology in LDE-aware analog sizing optimization.

As the primary second-order effect, parasitic issues have to be seriously addressed when synthesizing high-performance analog and RF integrated circuits (ICs). In this article, a two-phase hybrid sizing methodology for analog and RF ICs is proposed to take into account parasitic effect in the early design stage. It involves symbolic modeling and mixed-integer nonlinear programming (MINLP) in the first phase, and a many-objective evolutionary algorithm (many-OEA)-based sizing refiner in the second phase. With the aid of our proposed current density factor and piecewise curve fitting technique, the g m / I D concept, which is typically utilized to solve the analog circuit design problem, can provide theoretical support to our accurate symbolic modeling. Thus, the intrinsic and interconnect parasitics can be accurately considered in our work with moderate modeling effort. A variety of electrical, geometric, and parasitic (including parasitic mismatch) constraints can be conveniently integrated into our MINLP problem formulation. Moreover, numerical simulations are embedded into the many-OEA-based sizing phase, which is able to tackle floorplan co-optimization. With such dynamic floorplan variation, the parasitics accuracy can be sustained along the evolution. The experimental results demonstrate high efficacy of our proposed parasitic-aware hybrid sizing methodology.

Layout-dependent effects (LDEs) as one type of second-order effects in addition to parasitics, the primary second-order effect, are considered in our proposed two-stage hybrid sizing methodology for analog circuits. The first-stage sizing optimization is realized by using gm/ID-based symbolic modeling and nonlinear programming. A many-objective evolutionary algorithm based sizing refiner works for the second-stage optimization. MOSFET characterization and considerations of intrinsic and interconnect parasitics as well as LDEs are addressed progressively throughout the proposed hybrid sizing flow. Finally, the experimental results demonstrate high efficacy of our proposed gm/ID-based parasitic-aware and LDE-aware two-stage sizing methodology.

Evaluating the performance of schematic-level un-sized circuits is always a challenging task within the automated analog circuit synthesis process. One has to trade accuracy for efficiency in order to maintain efficient synthesis. This paper presents a new method of fast performance evaluation, which can be applied to general analog circuit synthesis frameworks. We propose to integrate graph-based symbolic analysis with the curve-fitting technique by using the gm/lDmethodology. Both linear programming and nonlinear programming are utilized to validate the feasibility of un-sized circuit topology with reference to the defined specifications. Our experimental results indicate high efficacy of the proposed method. It can significantly reduce the entire circuit synthesis time by leaving a small number of circuit topologies for detailed sizing and further evaluation.

In this paper, an efficient parasitic-aware geometric programming and many-objective evolution algorithm based two - phase hybrid sizing methodology is presented. It considers circuit performance constraints and layout parasitics simultaneously within a concurrent process by using convex optimization in the first phase, and knowledge-driven heuristic refinement in the second phase. The proposed method has been used to optimize several analog and RF circuits in different CMOS technologies with high efficacy demonstrated.