With the development of flash technology, the increasing throughput gap betweennandflash memory (NFM) arrays and the I/O interface has become a performance bottleneck for NFM-based solid-state drives (SSDs). Multilevel parallelism techniques have been employed on modern SSDs to meet the challenge of increasing demands for bandwidth in I/O-intensive workloads. However, conventional parallel methods only monitor the status of ways, resulting in the “idle bubble”—idle time of the dies cannot execute subsequent operations until all the dies in the way complete command execution. This issue limits the resource utilization and performance of SSDs. To minimize the idle bubble, we propose priority-based out-of-order scheduling and fine-grain status polling (POFGSP). The priority-based out-of-order scheduling relaxes constraints on command execution order and schedules commands with the same execution time to be executed in parallel. Therefore, the scheduler reduces these idle bubbles caused by differences in command execution times. Moreover, the fine-grain status polling approach polls the die-level status during the interface’s idle time, reducing idle bubbles with accurate status. Compared to state-of-the-art schedulers, our POFGSP approach can reduce request response time by 35.6% under real-world cloud block storage workloads and improve the SSD system’s maximum bandwidth by 8.7%–74.9%.

Quad-level cell (QLC) has received significant attention recently due to its extremely high storage capacity. However, because of its poor reliability, QLC-based solid-state drives (SSDs) require a two-step programming to reduce the layer interference. But during the interval between two programming steps on the same wordline (WL), data could be invalidated from update operations, leading to invalid programming and degraded performance. To mitigate the performance loss, we propose the NV-APP scheme to minimize the program and verify pulses during the second-step programming. NV-APP integrates the no-verify (NV) scheme and the adaptive pulse programming scheme (APP). The NV scheme omits verify pulses of invalid verify voltages. The APP scheme adaptively increases the programming step voltage$(V_{\mathrm { step}})$to accelerate cells’ threshold voltage shift, reducing the number of both program and verify pulses. Device-level simulation results show that the NV-APP scheme reduces the total number of program pulses by an average of 27.03% and verify pulses by an average of 48.70% across various invalid cases during the second-step programming. Based on a modified 3-D QLC SSD simulator with typical traces, the experiments demonstrate that our scheme reduces two-step programming time by an average of 17% on partially invalid WLs, close to the 19.8% reduction achieved by the ideal scheme with no performance loss.

Triple-level cell NAND flash memory is widely used today due to its higher storage density and capacity. However, with the increase in the storage density, lower reliability results in more read times for flash memory and significantly reduces the read performance. In order to avoid unnecessary read operations, this article proposes a hard decision–soft decoding method called location information-assisted decoding (LIAD) method, which determines the additional information required for decoding by mutual information, and then transmits the required information to correct the log-likelihood ratio (LLR). Different from the conventional LLR correction algorithm, this method does not require additional read operations and correct data. Only using sensing results, our method can reduce uncorrectable error bit rate (UBER) by up to 99%, and the system read latency under SSDsim (Hu et al. 2011) simulation can be reduced by up to 53%.

Although NAND flash memory does a lot of work in effectively using error correcting code (ECC) to reduce uncorrectable bit error rate (UBER). However, if the frame error rate (FER) is not reduced, the lower UBER cannot effectively reduce the read latency of the flash memory system. This phenomenon is especially evident at the end of the flash memory lifetime, where conventional methods significantly reduce the UBER but not to zero, and the remaining error bits are still evenly distributed throughout the flash memory page, resulting in a significant increase in read latency. In this article, an interleaved LDPC decoding scheme is proposed. By re-evaluating the flash memory channel during the decoding process, the codewords in the flash memory page are corrected frame by frame, and the problem of high FER is solved at the end of the flash memory lifetime. Compared with the conventional algorithm, the proposed method can reduce the FER by up to 34%, reduce the average decoding iterations by 63.4%, and reduce the read latency by up to 65%.

Layout hotspot detection is one of the most important issues for the reliability enhancement of integrated circuits. Machine learning-based hotspot detectors have shown their advantages of efficiency and generalization compared with computationally intensive lithography process simulation. However, most machine learning-based hotspot detectors only accept layout clips of fixed size as input with the potential defect whose location is restricted at the center of each clip. Therefore, they cannot be used directly for multiple hotspots detection in a large area, which occurs frequently in real design cases. In this article, we build a new end-to-end hotspot detector based on a fully convolutional network, which has the flexibility of detecting a various number of hotspots in a layout of any size at one time. Moreover, we also develop a transfer learning scheme matching our proposed detector network, which can reduce the requirement of sample number when setting up a new model for a more advanced technology node. The experimental results demonstrate our proposed hotspot detector outstanding among state-of-the-art works and the transfer learning scheme is effective.

This paper presents the design and implementation of memory-based fast Fourier transform (FFT) processors with generalized efficient, conflict-free address schemes. We unified the conflict-free address schemes of three different FFT lengths, including the single-power points, the common nonsingle-power points, and the nonsingle-power points applied with a prime factor algorithm. Though the three cases differ in terms of decomposition, they are all compatible with memory-based architecture by the way of the proposed address schemes. Moreover, the decomposition algorithm utilizes a method, named high-radix-small-butterfly (HRSB), to decrease the computation cycles and eliminate the complexity of the processing engine. In addition, an efficient index generator, a simplified multipath delay commutator engine, and a unified Winograd Fourier transform algorithm butterfly core were also designed. We designed two FFT examples in long-term evolution system to verify the availability of the address scheme, including a 2n(128-2048)-point FFT unit and a 35 different point (12-1296) DFT unit. Compared with previous works with similar address schemes, this paper supports more generalized lengths and achieves more flexible throughput.

A 95 dB dynamic range automatic gain control (AGC) circuits and systems for Multi-standard Digital TV (DTV) tuner has been presented. A novel automatic gain control method composed of RFAGC and IFAGC is proposed with improved SNR. A wideband single-ended LNA based on current-reuse technique with low temperature variation is proposed. The complete AGC circuits are fabricated in six-metal 0.18-μm CMOS technology and consume DC current of 32.5 mA from a 1.8 V supply. The RF front-end circuit achieves 90 dB maximum gain, 95 dB gain control range, a 4 dB noise figure and an IIP3 higher than -28 dBm at the maximum gain.

A fully integrated direct up-conversion transmitter for Chinese electronic toll collection system (ETCS) is presented in a 0.18um CMOS process. Improved isolation between power amplifier (PA) and voltage-control oscillator (VCO) is achieved by configuring the VCO frequency to be 2/3 transmission frequency. A 5.8GHz mixer with an automatic amplitude control (AAC) loop is proposed to obtain better amplitude shift keying (ASK) performance. The occupied bandwidth of the transmitter is optimized by digital filtering. A high-linearity ASK modulator translates the base-band signal to carrier frequency and a two-stage class-A and class-AB PA is adopted to obtain sufficient efficiency and relatively high linearity. The transmitter consumes only 99mW with 1.8V supply voltage to meet the low-power demand of Chinese ETCS and carries a single-ended 3.2dBm output power. Under 1.024Mbps data rate, the eye-opening is better than 91% and the transmitter achieves -58.2dBc adjacent channel power ratio (ACPR) and 1.46MHz occupied bandwidth.