The search for energy efficient circuital implementations of neural networks has led to the exploration of phase-change memory (PCM) devices as their synaptic element, with the advantage of compact size and compatibility with CMOS fabrication technologies. In this work, we describe a methodology that, starting from measurements performed on a set of real PCM devices, enables the training of a neural network. The core of the procedure is the creation of a computational model, sufficiently general to include the effect of unwanted non-idealities, such as the voltage dependence of the conductances and the presence of surrounding circuitry. Results show that, depending on the task at hand, a different level of accuracy is required in the PCM model applied at train-time to match the performance of a traditional, reference network. Moreover, the trained networks are robust to the perturbation of the weight values, up to 10% standard deviation, with performance losses within 3.5% for the accuracy in the classification task being considered and an increase of the regression RMS error by 0.014 in a second task. The considered perturbation is compatible with the performance of state-of-the-art PCM programming techniques.

Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.

Leakage discharge currents represent one of the most detrimental factors for the maximum hold time in analog sample-and-hold circuits. Apart from the obvious passive solution of enlarging the sampling capacitor, alternatives based on active circuits have been proposed. We focus here on an existing solution which has proven to be effective in reducing the leakage discharge, hence extending the hold time, by a factor of 20. Being based on a feedback circuit built around the hold capacitor, it is paramount to understand its stability properties. This work tries to close the gap by analyzing the closed-loop stability of the nominal circuit. Classical control systems techniques are employed to thoroughly analyze the dynamic behaviour of the feedback circuit, highlighting the detrimental effect of device mismatches.

Performance in analog integrated circuits strongly depends on the mismatch between nominally identical devices. In this work we derive closed-form asymptotic expressions describing mismatch variance in multifinger structures, under the assumption of Gaussian autocorrelation for the mismatch-generating stochastic process. The analysis is performed on inter-digitated geometries, eventually modified to make them common-centroid. Comparison with the numerical results provided by an independent model validates the theoretical expressions presented here.