Demo Data from EDBT 2026 / reviewers in the wild / expert
Elias Wald
dblp:195/6457
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
concurrent data structures |
0.3 | 1 | 2017 | POSTER: State Teleportation via Hardware Transactional Memory · PPoPP 2017 |
Parallel and multicore computing
concurrent programming |
0.3 | 1 | 2017 | POSTER: State Teleportation via Hardware Transactional Memory · PPoPP 2017 |
Parallel and multicore computing › transactional memory
hardware transactional memory |
0.3 | 1 | 2017 | POSTER: State Teleportation via Hardware Transactional Memory · PPoPP 2017 |
Parallel and multicore computing › concurrent data structures
hazard pointers |
0.3 | 1 | 2017 | POSTER: State Teleportation via Hardware Transactional Memory · PPoPP 2017 |
Parallel and multicore computing › concurrent data structures
lock-free data structures |
0.3 | 1 | 2017 | POSTER: State Teleportation via Hardware Transactional Memory · PPoPP 2017 |
Parallel and multicore computing
transactional memory |
0.3 | 1 | 2017 | POSTER: State Teleportation via Hardware Transactional Memory · PPoPP 2017 |
Parallel and multicore computing › synchronization
fine-grained locking |
0.1 | 1 | 2017 | POSTER: State Teleportation via Hardware Transactional Memory · PPoPP 2017 |
Methods — techniques the papers use, named apart from their topics
state teleportation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | The Teleportation Design Pattern for Hardware Transactional MemoryabstractWe identify a design pattern for concurrent data structures, called teleportation, that uses best- effort hardware transactional memory to speed up certain kinds of legacy concurrent data struc- tures. Teleportation unifies and explains several existing data structure designs, and it serves as the basis for novel approaches to reducing the memory traffic associated with fine-grained locking, and with hazard pointer management for memory reclamation. Nachshon Cohen, Maurice Herlihy, Erez Petrank, Elias Wald |
OPODIS | 4 |
| 2017 | POSTER: State Teleportation via Hardware Transactional MemoryabstractState teleportation is a new technique for exploiting hardware transactional memory (HTM) to improve existing synchronization and memory management schemes for highly-concurrent data structures. When applied to fine-grained locking, a thread holding the lock for a node launches a hardware transaction that traverses multiple successor nodes, acquires the lock for the last node reached, and releases the lock on the starting node, skipping lock acquisitions for intermediate nodes. When applied to lock-free data structures, a thread visiting a node protected by a hazard pointer launches a hardware transaction that traverses multiple successor nodes, and publishes the hazard pointer only for the last node reached, skipping the memory barriers needed to publish intermediate hazard pointers. Experimental results show that these applications of state teleportation can substantially increase the performance of both lock-based and lock-free data structures. Nachshon Cohen, Maurice Herlihy, Erez Petrank, Elias Wald |
PPoPP | 4 |