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Luhao Liu

dblp:196/0922 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 88% Interconnection networks and networks-on-chip · 12%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA accelerator
0.912025
Coyote v2: Raising the Level of Abstraction for Data Center FPGAs · SOSP 2025
Reconfigurable computing and FPGAs › dynamic reconfiguration
partial reconfiguration
0.912025
Coyote v2: Raising the Level of Abstraction for Data Center FPGAs · SOSP 2025
Reconfigurable computing and FPGAs
FPGA-based neural network inference
0.312025
Coyote v2: Raising the Level of Abstraction for Data Center FPGAs · SOSP 2025
YearPublicationVenuePosition
2025 Task Offloading Based on Incomplete System Information in Cloud-Edge-End Collaborative Architecture
abstract
The cloud-edge-end network architecture is an emerging model that integrates the advantages of both cloud and edge computing to effectively enhance the system's computational capacity. However, a key challenge within this architecture is how to efficiently offload tasks to fully utilize distributed computing resources while minimizing task execution latency. Most existing approaches assume that complete system information can be obtained in real time to make task offloading decisions. However, this assumption often leads to high communication overhead in practical applications, and the system's dynamic nature can make obtaining complete information impractical. To address this challenge, we propose a partially observable task offloading algorithm (POTO) that makes efficient offloading decisions based on partial system information. First, we model the task offloading problem as a partially observable Markov decision process (POMDP) and design an encoder using a Long Short-Term Memory (LSTM) network to extract system state information from past offloading decisions. Finally, we improve the actor-critic algorithm with a clipping mechanism and action masking to achieve an efficient offloading strategy. Experimental results show that POTO achieves a 95% task success offloading rate while reducing latency by at least 14% compared to other algorithms. Furthermore, even with partial system information, POTO performs at 96% of the effectiveness of algorithms utilizing complete system information.
Luhao Liu, Mengyang He
CSCWD1
2025 Coyote v2: Raising the Level of Abstraction for Data Center FPGAs
abstract
In the trend towards hardware specialization, FPGAs play a dual role as accelerators for offloading, e.g., network virtualization, and as a vehicle for prototyping and exploring hardware designs. While FPGAs offer versatility and performance, integrating them in larger systems remains challenging. Thus, recent efforts have focused on raising the level of abstraction through better interfaces and high-level programming languages. Yet, there is still quite some room for improvement. In this paper, we present Coyote v2, an open-source FPGA shell built with a novel, three-layer hierarchical design supporting dynamic partial reconfiguration of services and user logic, with a unified logic interface, and high-level software abstractions which facilitate application deployment, multi-tenancy and transparent workload pipelining. Experimental results indicate Coyote v2 reduces synthesis times between 15% and 20% and run-time reconfiguration times by an order of magnitude, when compared to existing systems. We also demonstrate the advantages of Coyote v2 by deploying several realistic applications, including HyperLogLog cardinality estimation, AES encryption, and neural network inference. Finally, Coyote v2 places a great deal of emphasis on integration with real systems through reusable and reconfigurable services, including a fully RoCE v2-compliant networking stack, a shared virtual memory model with the host, and a DMA engine between FPGAs and GPUs. We demonstrate these features by, e.g., seamlessly deploying an FPGA-accelerated neural network from Python.
Benjamin Ramhorst, Dario Korolija, Maximilian Jakob Heer, Jonas Dann, Luhao Liu, Gustavo Alonso
SOSP5