This paper presents a highly dense SRAM-based computation-in-memory (CIM) architecture designed for area-efficient AI acceleration. The proposed architecture leverages charge redistribution in a capacitor-based CIM design to enhance linearity, effectively mitigating the impact of variable parasitic capacitance inherent in FETs. To address the dynamic range mismatch between the CIM array and the ADC, a dynamic range calibration scheme is introduced. Recognizing the significant area overhead of ADCs in CIM, this work also proposes an area-efficient SR-latch-based cap-DAC driver. Furthermore, this work compares and analyzes various ADC comparator reference types, ultimately proposing individual reference columns with global drivers to achieve both ADC symmetry and improved area/power efficiency. Fabricated using a 65nm LP process, the prototype occupies a core area of 0.265 mm2, comprising a 108kb ($432\times 256$) SRAM-CIM array and 256 column-by-column ADCs with peripherals. This design achieves a weight density of 415.4 kb/mm2. By employing column-by-column ADCs, which avoid the throughput limitations of ADC sharing, the prototype achieves an energy efficiency of 95.4 TOPS/W and a throughput of 813.6 GOPS. The resulting area and energy-efficient architecture achieves a SWaP (space, watt, and performance) figure-of-merit of 39.63 TOPS/W$\times $Mb/mm2.

Through-Silicon Vias (TSVs) are essential parts of interconnects in 3-D ICs such as high bandwidth memory (HBM). TSV defects from fabrication or electromigration can increase the resistance of defective TSVs and degrade signal integrity. As many TSVs are implemented in HBMs, effective testing of TSVs and identifying defective TSVs become evermore significant. In this paper, we propose a faulty TSV detection scheme for identifying the locations of faulty TSVs without time-consuming manual probing. TSV conditions are sensed by transmission signal between transceivers. Such signal will also operate in transition-time-to-voltage converter and sensor for TSV condition checking. The location of faulty TSV indication signals from the sensors in each core die will transmit back to the base logic die for further operations. Moreover, the proposed detector can detect faulty TSVs while the transceivers are operating.

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM1, FoM2, and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively.