EDBT 2026 Demo / reviewers in the wild / expert
Jiayoon Ru
dblp:196/1859 · also Jiayoon Zhiyu Ru
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2025
0009-0009-5045-4506ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | A Compact Cost-Effective NB-IoT System-in-Package With Integrated RF Front-End IPD and TX/RX Gain Self-CalibrationabstractA compact cost-effective Narrowband Internet-of-Things (NB-IoT) System-in-Package (SiP) in mass production is implemented in 55nm CMOS and Integrated Passive Device (IPD) process. The RF front-end components, i.e., inductors and capacitors, are integrated into an IPD die to reduce the Bill of Material (BOM) cost. Notably, the design eliminated the necessity of the antenna switches (ANTSW). On the IPD die, a diplexer is employed to separate the low-band (LB) and high-band (HB) paths, while in each band, the transmitter (TX) and the receiver (RX) share a common RF low pass filter through a co-matching network. To ensure robust performance, CMOS switches are placed at the PA’s drain and the LNA’s input, protecting the LNA core devices from breaking down and tuning essential impedance matching for both TX and RX. The built-in self-calibration scheme enables the chip to calibrate its TX/RX gain autonomously and flexibly, eliminating the use of external equipment therefore reducing the cost at the module production line. The NB-IoT SoC is integrated with the IPD die in a$7\times 7$QFN package. The system operates across the NB-IoT bands from 699MHz to 2200MHz (the CMOS chip supports 450MHz to 2200MHz), with transmitter’s Psatover +26dBm and achieving the HD2/HD3 below −36dBm when transmitting at +23dBm. The self-calibration scheme improves TX LO leakage and image by more than 15dB and ensures TX/RX gain accuracy within +/−0.5dB across the band and gain states. Haopei Deng, Jiayi Ye, Zexue Liu, Danping Li, Xiaoyu Fu, Yongfu Li 0002, Jiayoon Ru, Jianhong Xiao |
IEEE Trans. Circuits Syst. I Regul. Pap. | 11 |
| 2023 | An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT ApplicationsabstractThis paper proposes an information-aware (IA) adaptive data acquisition (ADA) system for the Internet of Things (IoT) applications. The system can obtain valid information adaptively thanks to 1) signal-dependent full-scale feature tracks the amplitude-domain activity of the event; 2) level-crossing (LC) ADC with slope detector delivers the time-domain activity; 3) the IA algorithm determines the quantization resolution according to the detected signal activities. The proposed clock-free event-driven ADA system can reject the redundant data, and compress the valid data from the source, thus saving its power and the power of subsequent data-processing systems. The long-term average power consumption of the system is 128 nW, the resolution varies from 3 to 7 bits according to the input signal state. Compared with conventional ADCs, LC-ADC can compress the data by 2.5x [1]. Further, the proposed system has 15x higher compression ratio (CR) than that of LC-ADC. Yiqi Jing, Zhixuan Wang, Linxiao Shen, Yihan Zhang 0002, Jiayoon Ru, Le Ye |
ISCAS | 6 |
| 2023 | An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory TechniqueabstractThis article presents a clock-free spiking neural network (SNN) intelligent inference engine (IIE) for artificial intelligence of things (AIoT) sensor nodes, which often operate in random-sparse-event (RSE) scenarios. The IIE drastically reduces the system’s long-term average (LTA) power consumption, improves energy efficiency, and achieves microsecond level inference latency. Three techniques are proposed: 1) A clock-free SNN architecture without clock tree, frame generator, and arbiter, is driven by the output spikes, which are encoded with level-crossing (LC) sampling method; the circuit activity is completely related to event activity and spike rates, dramatically reducing the overall power consumption and latency. 2) The bioinspired leaky-integrate-fire (LIF) neurons directly extract the time-domain information from asynchronous spikes, reducing the network size and number of operations. 3) The computing-in-memory (CIM) and mixed-signal synapse-neuron circuits are employed to increase the SNN parallelism and avoid weight movements, thus improving the energy efficiency and response speed. The measured LTA power is bounded at 82 nW while the event-driven chip is on call and waiting for events; the energy efficiency is 0.53 pJ per synapse operation (SOP), only 1/3 that of state-of-the-art methods at 4bit weights even with 180 nm technology. We demonstrate electrocardiogram (ECG) recognition as a typical AIoT application, and the power consumption is less than 350 nW. The measured accuracy of abnormal ECG detection is 90.5%. Moreover, the latency is only$40 \mu \text{s}$to realize real-time NN inference. This work provides an effective solution for AIoT nodes that require both ultralow power and fast response. Ying Liu 0069, Yufei Ma 0002, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru Huang 0001, Le Ye |
IEEE Trans. Circuits Syst. I Regul. Pap. | 6 |