Split capacitor digital-to-analog converters (split-CDACs) are a promising method to reduce area but face challenges with parasitic sensitivity in high-resolution settings for successive approximation register analog-to-digital converters (SAR ADCs) design. This article introduces a split-CDAC design for improving area efficiency for higher bit resolution by reducing parasitic sensitivity and mismatch. A fundamental reason for the increased parasitic sensitivity stems from the fractional sizing of the bridge capacitor and a small redundant capacitor at the split node. The proposed split-CDAC uses a unit capacitor-based bridge capacitor and a proportionally scaled large redundant unit capacitor, which minimizes these effects to a large extent while achieving linearity. It achieves six times better parasitic sensitivity than a conventional split-CDAC by using six-unit capacitors as a bridge capacitor and 12 times better area efficiency than the conventional binary-weighted CDAC. The proposed fully common-centroided and shielded unit capacitor array, implemented in a 65 nm CMOS process, effectively reduces parasitic and mismatch sensitivity using a simple layout structure. The implementation achieves an INL of less than 1.2 LSB, measured across 21 chips, without mismatch calibration and opens new possibilities for high-precision applications across diverse domains.

This brief presents a nano-watt wake-up timer implemented mainly through digital synthesis. By performing successive subharmonic frequency locks between two leakage-based digitally controlled oscillators (DCOs) and repeatedly switching their roles, the period of the timer can be locked to a scaled RC time, enabling low-frequency generation without the need for substantial RC values. The proposed frequency-lock scheme is applied to design a 360 Hz timer. The implemented timer in a 0.18-$\mu $m CMOS process consumes 9.6 nW and shows a standard deviation of 1.36% without the need for extensive external trimming, mainly due to intra-wafer process variation. The measured supply and temperature sensitivities are 0.32%/V and 395 ppm/°C, respectively.

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This article proposes a circuit architecture and design strategy of a low-noise oscillator based on the distributedRCnetwork. The distributedRCnetwork receives a differential step input and propagates the true phase through the resistive path while the complementary phase through the capacitive path. It effectively suppresses the effect of noise by increasing the signal transition slope at the time of interest. It is achieved by embedding a bandpass characteristic with a phase delay of$\pi $. A 358-kHz quadrature oscillator with a fourth-stageRCnetwork is implemented using the 0.18-$\mu \text{m}$CMOS process. It achieves an figure of merit (FoM) of −161.2 dBc/Hz at a 100-Hz offset with a stable 20-dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm.

For the first time, we prove that 7.8-Gb/s single-ended signaling through a highly reflective channel is feasible at low energy cost by an energy-efficient many-tap decision feedback equalization (DFE) receiver (RX). The reported data rate of 7.8 Gb/s is the fastest data rate that has been achieved through a single-ended highly reflective channel that has more than five taps of postcursor reflective intersymbol interference. Compared with the prior arts, the target multidrop has the most in-band notches: ten notches. To compensate for large reflection by many notches, the RX exploits the DFE with the largest tap count of 20 that has been never used in single-ended signaling before. Low-power circuit techniques such as a current-integrating summer and double-tail sense amplifiers were adequately adopted and engineered to reduce large power dissipation by many taps. The RX was fabricated in a 65-nm CMOS technology and occupies only 0.014 mm2. The energy efficiency was measured to be only 2.9 pJ/b at 7.8 Gb/s with 0.9-V supply, proving that fast single-ended signaling through a highly reflective channel is feasible at low energy cost by many-tap DFE if low-power circuit techniques are adequately applied. The horizontal and vertical eye sizes were measured to be 0.12 UI and 34 mV, respectively, at a bit error rate of-12.

This paper presents an amplifier-less and digital-intensive current-to-digital converter for biosensors. The proposed circuit achieves a first-order noise shaping of the quantization error without any continuous-time feedback circuit. Also, it minimizes static power consumption by employing a single-ended current-steering digital-to-analog converter (DAC) which flows only the same current as the input. The effect of dynamic switching noise become input-independent constant by adopting switching averaging algorithm. The implemented circuit in 0.35pm CMOS converts an input range of 2.8pA to 15b digital output in about 4ms, while consuming 16.8pW.